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ASSURA 3.1.6 - errors on input/output pins

Hi,
I am using ASSURA for the first time, and I am having some problems, let me explain. I am designing a pixel matrix, I have done the layout for one single pixel, and I am trying to run DRC with ASSURA on this single pixel layout. For the pixel input/output nets I have defined serveral pins using the Create->Pin->shape pin options of Cadence Virtuoso Layout tool. The problem is that assura doesn't seems to recognize these pins. For example, I have defined a vdd! pin connected to the NTUB layer, but ASSURA keeps giving me a warning of HOT NTUB. For the pins defined at the gates of the transistors asssura gives a warning saying 'floating gate not connected...'.

Do you know how should I do to perform a DRC with ASSURA on my pixel layout without receiving these errors/warnings? Is there a way to do it?

Thanks and regards,
Pedro

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yoyega over 15 years ago

Ok, I understand, I thought it could be something generic about ASSURA. I will try to contact the technical support of the DRC rules file provider then.

Thank you very much for your reply Andrew,
Pedro
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yoyega over 15 years ago

Ok, I understand, I thought it could be something generic about ASSURA. I will try to contact the technical support of the DRC rules file provider then.

Thank you very much for your reply Andrew,
Pedro
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