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connections to abstract not verified by Assura LVS - what's wrong?

TrevorB

Hi,

We are using an IP block from our foundry in our chip.  The IP block is located below the top level of the hierarchy.  And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.

Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain!  That's no good...

What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?

Thanks!

Trevor

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  • shumble1

    This post was really valuable.  We have been running into the same problem with an empty schematic, but had not yet determined the best method for fixing this problem. 

     

    We are on Assura41USR1_HF14, and the empty pins-only schematic was still not netlisted correctly.  Maybe it was there on HF3, but by the time it got to HF14, it has disappeared again. 

     

    I'm going to try the workaround for copying the symbol to the auLVS view.  This will probably be the best solution for us at this time.

     

Reply
  • shumble1

    This post was really valuable.  We have been running into the same problem with an empty schematic, but had not yet determined the best method for fixing this problem. 

     

    We are on Assura41USR1_HF14, and the empty pins-only schematic was still not netlisted correctly.  Maybe it was there on HF3, but by the time it got to HF14, it has disappeared again. 

     

    I'm going to try the workaround for copying the symbol to the auLVS view.  This will probably be the best solution for us at this time.

     

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