We are using an IP block from our foundry in our chip. The IP block is located below the top level of the hierarchy. And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.
Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain! That's no good...
What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?
I tried both HF14 and creating an "auLvs" view and neither of them worked with our cell.
The symbol we use has pins that are busses for example PA<8:0>. It seems that when Assura runs, it does not recognize any pins that are labeled as busses. Is there a workaround for this?