We are using an IP block from our foundry in our chip. The IP block is located below the top level of the hierarchy. And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.
Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain! That's no good...
What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?
Hi shumble1If you are seeing netlisting error due to bus notations for the pins, this issue has already been resolved and the fix is in Assura41USR2. USR2 is the immediate version after Assura41USR1_HF14. You can of course also use the latest version Assura41USR2_HF1. The fix is in it too. Previously Assura is unable to correctly expand a bus notation in cdf "termOrder" property and a workaround was to manually expand it in the cdf form. Eg.Original pin name in "termOrder" property in cdf form:abc<0:3>Workaround:abc<0> abc<1> abc<2> abc<3>Would you please try Assura41USR2_HF1 to see if it resolves your problem? If it does not, kindly post the Assura log file that contains the error message.ThanksQuek