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connections to abstract not verified by Assura LVS - what's wrong?

TrevorB

Hi,

We are using an IP block from our foundry in our chip.  The IP block is located below the top level of the hierarchy.  And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.

Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain!  That's no good...

What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?

Thanks!

Trevor

Parents
  • Quek
    Hi Trevor

    This should not be happening. Assura will verfied connections and pins for blackboxes. If you check design.erc file in the lvs run directory, do you see pins being created for the ip block?

    Would you please provide the following info?
    a. Input layout type: gds2 or df2?
    b. Do pinLayer and pinText cmds exist in extract.rul file?
    c. Output of "assura -W" cmd in a terminal window

    Please see the section "Extracting Cells as Black Box Cells" in the Assura Developer's Guide for more info on blackbox methodology.
    linux>xpdf $ASSURAHOME/doc/assuradev/assuradev.pdf &

    Best regards
    Quek
Reply
  • Quek
    Hi Trevor

    This should not be happening. Assura will verfied connections and pins for blackboxes. If you check design.erc file in the lvs run directory, do you see pins being created for the ip block?

    Would you please provide the following info?
    a. Input layout type: gds2 or df2?
    b. Do pinLayer and pinText cmds exist in extract.rul file?
    c. Output of "assura -W" cmd in a terminal window

    Please see the section "Extracting Cells as Black Box Cells" in the Assura Developer's Guide for more info on blackbox methodology.
    linux>xpdf $ASSURAHOME/doc/assuradev/assuradev.pdf &

    Best regards
    Quek
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