connections to abstract not verified by Assura LVS - what's wrong?

Hi Quek,

Thanks for your reply.  To answer your questions:

1) I cannot find the IP block's cellName even mentioned in the design.erc file.

2) The layout and schematic are both df2 - no GDS2.

3) I found the following rules in my extract.rul file:

;; 
;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;; text layer 
;; 
   POLY1_pintext = textToPin( "PIN"  type( "poly1")) 
   MET1_pintext = textToPin( "PIN"  type( "metal1")) 
   MET2_pintext = textToPin( "PIN"  type( "metal2")) 
   MET3_pintext = textToPin( "PIN"  type( "metal3")) 
   MET4_pintext = textToPin( "PIN"  type( "metal4")) 
   PAD_pintext = textToPin( "PIN" type( "pad")) 
;;
;; symbolic pins for macro LVS and RCX
;; 
   POLY1_sympin = pinLayer( "POLY1" type( "pin")) 
   MET1_sympin = pinLayer( "MET1" type( "pin")) 
   MET2_sympin = pinLayer( "MET2" type( "pin")) 
   MET3_sympin = pinLayer( "MET3" type( "pin")) 
   MET4_sympin = pinLayer( "MET4" type( "pin")) 

;; 
;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;; pinPurpose layer (only drc) 
;; 
   POLY1_pinPurpose = layer( "POLY1" type( "pin")) 
   MET1_pinPurpose = layer( "MET1" type( "pin")) 
   MET2_pinPurpose = layer( "MET2" type( "pin")) 
   MET3_pinPurpose = layer( "MET3" type( "pin")) 
   MET4_pinPurpose = layer( "MET4" type( "pin")) 
   PAD_pinPurpose = layer( "PAD" type( "pin"))

Using this PDK, for general pin designation, we only have to label the drawing shapes using layer, "PIN", purpose, "<metal_layer>", as indicated above.  However, inside the IP block layout, the pin shape also exists as a df2 "terminal".  So, it should be covered both ways.

4) The Assura version is:

$ assura -W
sub-version 3.2_USR2_HF11

$ assura -V
@(#)$CDS: assura version av3.2:Production:dfII5.1.41:5.10.41.500.6.130 06/29/2009 04:29 (logavt05) $

5) I have read the section you described, plus the related one in the user's guide, and I have tried the following statements in my runs:

Attempt #1: 

blackBox("MY_IP_BLOCK_CELL_NAME")

Attempt #2:

blackBox("MY_IP_BLOCK_CELL_NAME" sch)
blackBox("MY_IP_BLOCK_CELL_NAME" lay)

Strangely, both runs complain about not being able to find the cell in the design hierarchy, although I clearly see the cellName being used in both designs. ... Incidentally, for testing purposes, I am running LVS at a lower level of the chip, in which the IP block exists as a top level cell.  I don't know if that makes a difference...

Maybe the extract rules need some help, since neither I nor Assura can find the cell in Assura's schematic or layout netlist?

Thanks!

Trevor

Hi Quek,

Thanks for your reply.  To answer your questions:

1) I cannot find the IP block's cellName even mentioned in the design.erc file.

2) The layout and schematic are both df2 - no GDS2.

3) I found the following rules in my extract.rul file:

;; 
;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;; text layer 
;; 
   POLY1_pintext = textToPin( "PIN"  type( "poly1")) 
   MET1_pintext = textToPin( "PIN"  type( "metal1")) 
   MET2_pintext = textToPin( "PIN"  type( "metal2")) 
   MET3_pintext = textToPin( "PIN"  type( "metal3")) 
   MET4_pintext = textToPin( "PIN"  type( "metal4")) 
   PAD_pintext = textToPin( "PIN" type( "pad")) 
;;
;; symbolic pins for macro LVS and RCX
;; 
   POLY1_sympin = pinLayer( "POLY1" type( "pin")) 
   MET1_sympin = pinLayer( "MET1" type( "pin")) 
   MET2_sympin = pinLayer( "MET2" type( "pin")) 
   MET3_sympin = pinLayer( "MET3" type( "pin")) 
   MET4_sympin = pinLayer( "MET4" type( "pin")) 

;; 
;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;; pinPurpose layer (only drc) 
;; 
   POLY1_pinPurpose = layer( "POLY1" type( "pin")) 
   MET1_pinPurpose = layer( "MET1" type( "pin")) 
   MET2_pinPurpose = layer( "MET2" type( "pin")) 
   MET3_pinPurpose = layer( "MET3" type( "pin")) 
   MET4_pinPurpose = layer( "MET4" type( "pin")) 
   PAD_pinPurpose = layer( "PAD" type( "pin"))

Using this PDK, for general pin designation, we only have to label the drawing shapes using layer, "PIN", purpose, "<metal_layer>", as indicated above.  However, inside the IP block layout, the pin shape also exists as a df2 "terminal".  So, it should be covered both ways.

4) The Assura version is:

$ assura -W
sub-version 3.2_USR2_HF11

$ assura -V
@(#)$CDS: assura version av3.2:Production:dfII5.1.41:5.10.41.500.6.130 06/29/2009 04:29 (logavt05) $

5) I have read the section you described, plus the related one in the user's guide, and I have tried the following statements in my runs:

Attempt #1: 

blackBox("MY_IP_BLOCK_CELL_NAME")

Attempt #2:

blackBox("MY_IP_BLOCK_CELL_NAME" sch)
blackBox("MY_IP_BLOCK_CELL_NAME" lay)

Strangely, both runs complain about not being able to find the cell in the design hierarchy, although I clearly see the cellName being used in both designs. ... Incidentally, for testing purposes, I am running LVS at a lower level of the chip, in which the IP block exists as a top level cell.  I don't know if that makes a difference...

Maybe the extract rules need some help, since neither I nor Assura can find the cell in Assura's schematic or layout netlist?

Thanks!

Trevor