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  3. connections to abstract not verified by Assura LVS - what...

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connections to abstract not verified by Assura LVS - what's wrong?

TrevorB
TrevorB over 15 years ago

Hi,

We are using an IP block from our foundry in our chip.  The IP block is located below the top level of the hierarchy.  And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.

Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain!  That's no good...

What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?

Thanks!

Trevor

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  • Quek
    Quek over 15 years ago
    Hi Trevor

    Thank you for the detail info. Here is what I think:

    a. Blackbox cell cannot be found by Assura
    - Try using blackbox("cellName viewName libName")

    b. erc file does not contain ip cell name
    - This definitely means that the blackbox pins have not been extracted correctly
    - Check if you have enabled cmds such as ?textPriOnly=t or ?textLevel=0:0
    - Pin must be extracted for the blackbox in order for it to be properly compared
    - Since your extract rule file only contains pinLayer and textToPin cmds, you should ensure that the text origin overlaps the dfII pin shapes. Otherwise the shapes will be extracted without pin names. This is usually not necessary if pinText cmds are present. pinText reads the names of the dfII pins
    - If your current ip block only contains dfII pins and not text, please place the appropriate text over the pins using the pin layer and its corresponding metal purpose

    >>>running LVS at a lower level of the chip, in which the IP block exists as a top level cell.
    I think perhaps what you meant is "running LVS at a lower level of the chip in which the IP block exists as a cell in the top level". This is ok. Blackboxes will work as long as they exist as cells and not as the top level cell being compared.

    The blackbox cell should appear in both schematic and layout netlists. For your case, it should be similar to the following in the layout vnl netlist:

    c "myIPblock layout myLib" BlackBox  VDD P      GND G      IN NONE    avC4 N(f)
     ;;
    * 4 pins
    * 4 nets
    * 0 instances

    In case you are checking the schematic and layout netlists using vldbToCdl cmd in a terminal window, please note that this cmd does not dump out the blackbox cells. Please use vldbToVnl instead:
    unix>vldbToVnl design.ldb > design.ldb.ascii
    unix>vldbToVnl design.sdb > design.sdb.ascii

    For your information, if the contents of the ip block is not important and need not be extracted by lvs, you can also use ?blackBoxCell cmd in avParameters. The difference is that blackBox cmd allows shapes to be extracted normally during lvs and hence even though the ip cell will not be compared, parasitics can subsequently still be extracted from it. ?blackBoxCell only allows pins and some blackbox shapes to be extracted and so the final result is a true blackbox, not only for lvs comparison but also for parasitic extraction.


    Best regards
    Quek
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  • Quek
    Quek over 15 years ago
    Hi Trevor

    Thank you for the detail info. Here is what I think:

    a. Blackbox cell cannot be found by Assura
    - Try using blackbox("cellName viewName libName")

    b. erc file does not contain ip cell name
    - This definitely means that the blackbox pins have not been extracted correctly
    - Check if you have enabled cmds such as ?textPriOnly=t or ?textLevel=0:0
    - Pin must be extracted for the blackbox in order for it to be properly compared
    - Since your extract rule file only contains pinLayer and textToPin cmds, you should ensure that the text origin overlaps the dfII pin shapes. Otherwise the shapes will be extracted without pin names. This is usually not necessary if pinText cmds are present. pinText reads the names of the dfII pins
    - If your current ip block only contains dfII pins and not text, please place the appropriate text over the pins using the pin layer and its corresponding metal purpose

    >>>running LVS at a lower level of the chip, in which the IP block exists as a top level cell.
    I think perhaps what you meant is "running LVS at a lower level of the chip in which the IP block exists as a cell in the top level". This is ok. Blackboxes will work as long as they exist as cells and not as the top level cell being compared.

    The blackbox cell should appear in both schematic and layout netlists. For your case, it should be similar to the following in the layout vnl netlist:

    c "myIPblock layout myLib" BlackBox  VDD P      GND G      IN NONE    avC4 N(f)
     ;;
    * 4 pins
    * 4 nets
    * 0 instances

    In case you are checking the schematic and layout netlists using vldbToCdl cmd in a terminal window, please note that this cmd does not dump out the blackbox cells. Please use vldbToVnl instead:
    unix>vldbToVnl design.ldb > design.ldb.ascii
    unix>vldbToVnl design.sdb > design.sdb.ascii

    For your information, if the contents of the ip block is not important and need not be extracted by lvs, you can also use ?blackBoxCell cmd in avParameters. The difference is that blackBox cmd allows shapes to be extracted normally during lvs and hence even though the ip cell will not be compared, parasitics can subsequently still be extracted from it. ?blackBoxCell only allows pins and some blackbox shapes to be extracted and so the final result is a true blackbox, not only for lvs comparison but also for parasitic extraction.


    Best regards
    Quek
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