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connections to abstract not verified by Assura LVS - what's wrong?

TrevorB

Hi,

We are using an IP block from our foundry in our chip.  The IP block is located below the top level of the hierarchy.  And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.

Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain!  That's no good...

What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?

Thanks!

Trevor

Parents

  • Hi Trevor

    A cellname can be short (simply the cellname) or long (with view and lib info). Please see the section on "Representing Cell and Device Names" in the Assura Developer's Guide. Actually the correct cmd is :

    blackBox("cellName viewName libName")

    and not:

    ?blackBox ("cellName viewName libName")

    textPriOnly and textLevel need not be used if they are not necessary. I will think more about your question and update you again. Would you please uploaded your log, cls, csm and erc files? Total of 4 files.

    Thanks
    Quek

Reply

  • Hi Trevor

    A cellname can be short (simply the cellname) or long (with view and lib info). Please see the section on "Representing Cell and Device Names" in the Assura Developer's Guide. Actually the correct cmd is :

    blackBox("cellName viewName libName")

    and not:

    ?blackBox ("cellName viewName libName")

    textPriOnly and textLevel need not be used if they are not necessary. I will think more about your question and update you again. Would you please uploaded your log, cls, csm and erc files? Total of 4 files.

    Thanks
    Quek

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