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connections to abstract not verified by Assura LVS - what's wrong?

TrevorB

Hi,

We are using an IP block from our foundry in our chip.  The IP block is located below the top level of the hierarchy.  And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.

Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain!  That's no good...

What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?

Thanks!

Trevor

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  • TrevorB

    I spoke with our foundry's support team, and I experimented some more.  I finally got it working.  Here's what I learned:

    1. The black box's schematic cannot be empty.  It must contain at least one device (cds_thru, presistor, some transistor, etc.).  If it does not, Assura LVS will prune it from the netlist, despite the blackBoxCell statement.  We also included the pins.
    2. Any global signals that are pinned out on the layout must also be pinned out on the black box's symbol.  If they are not, then them must be tied to some non-trivial device (cds_thru, presistor, some transistor, etc.) inside the black box's schematic; otherwise, they will not appear on the definition of the black box's pin boundary.
    3. The dummy devices used inside the black box's schematic are of no consequence, since they will be discared as the ignored guts of a "black box".
    4. I ultimately used "blackBoxCell" instead of "blackBox", although I imagine "blackBox" could be used somehow too...

    As an example, here are the guts of our dummy schematic for the black box:

    Dummy Schematic for Black Box block

    Thanks again for the help, Quek!

    HTH,

    Trevor

Reply
  • TrevorB

    I spoke with our foundry's support team, and I experimented some more.  I finally got it working.  Here's what I learned:

    1. The black box's schematic cannot be empty.  It must contain at least one device (cds_thru, presistor, some transistor, etc.).  If it does not, Assura LVS will prune it from the netlist, despite the blackBoxCell statement.  We also included the pins.
    2. Any global signals that are pinned out on the layout must also be pinned out on the black box's symbol.  If they are not, then them must be tied to some non-trivial device (cds_thru, presistor, some transistor, etc.) inside the black box's schematic; otherwise, they will not appear on the definition of the black box's pin boundary.
    3. The dummy devices used inside the black box's schematic are of no consequence, since they will be discared as the ignored guts of a "black box".
    4. I ultimately used "blackBoxCell" instead of "blackBox", although I imagine "blackBox" could be used somehow too...

    As an example, here are the guts of our dummy schematic for the black box:

    Dummy Schematic for Black Box block

    Thanks again for the help, Quek!

    HTH,

    Trevor

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