We are using an IP block from our foundry in our chip. The IP block is located below the top level of the hierarchy. And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.
Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain! That's no good...
What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?
Hi TrevorIt is good to know that the problem has been resolved. Actually your problem no longer exists from Assura41 onwards. Prior to Assura41, it is not possible for Assura to netlist an empty schematic that has only pins. The workaround is to copy the symbol view as "auLvs" view and then change the cdf componentName (Go to cdf form, press "simInfo" button and select auLvs simulator) to the cell name. This will also work, no components are needed inside the empty schematic. Only pins are necessary. I have confirmed what you are observing using Assura32USR2.If the latest Assura41USR1_HF3 is used, it is not necessary to create the auLvs view. The empty pins-only schematic will be netlisted correctly. If you have time, maybe you can switch to Assura41USR1_HF3 and give it a try.Thank you very much for the detail explanation. I think you have contributed a valuable post to the forum which will be helpful to other users. : )Best regardsQuek