I've got a problem when I run LVS with Calibre. The circuit extraction report gives me this warning:
WARNING: Invalid PATHCHK request "! LABELED": no LABELED nets present, operation aborted.
So the circuit extraction aborts, and I can't perform the parasitic extraction.
I inserted label for vdd and gnd, using the layer drawing of the same type of the path I labeled, but the problem didn't disappear. I made the pins using the layer pn, with a label using the layer M_CAD TT.
Do you know what is the problem?
Thanks a lot,
Calibre is by Mentor Graphics, not Cadence Design Systems. You might want to post this question on their forum.