Stats

Locked Locked
Replies 1
Subscribers 125
Views 17183
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

problems with calibre lvs

Francy over 15 years ago

Dear all.

I've got a problem when I run LVS with Calibre. The circuit extraction report gives me this warning:

WARNING: Invalid PATHCHK request "! LABELED": no LABELED nets present, operation aborted.

So the circuit extraction aborts, and I can't perform the parasitic extraction.

I inserted label for vdd and gnd, using the layer drawing of the same type of the path I labeled, but the problem didn't disappear. I made the pins using the layer pn, with a label using the layer M_CAD TT.

Do you know what is the problem?

Thanks a lot,

Francesca

tkhan over 15 years ago

Calibre is by Mentor Graphics, not Cadence Design Systems. You might want to post this question on their forum.
Cancel
Vote Up 0 Vote Down

Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.