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Extraction of parasitic parameters of a MOS transistor used like switch

Ueue
Ueue over 15 years ago

Dear all,

I need to have a precise estimation of the parasitic capacitances of my MOSFETs, used as switches. I was thinking, for the measure of capacitances to impose a voltage source with voltage Vs increasing linearly with time and measuring the current (proportional to the capacitances). So Vs=K*t. For example connecting the generator to the gate, and the other terminals to ground, I could measure the Cgd and Cgs. Is it a good method?

Thanks a lot,

Stefano

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  • IanX
    IanX over 11 years ago

    I have the same problems. I want to design a buffer chain. According to the design procedures from the book by Baker, I need to know the input capacitance of the inverter and the output capacitance of the inverter. What I try to do is do the DC analysis in cadence, then print the dc operating opoint. After that, we can see a lot of parameter listed in the table. 

    However, I felt a little confused. If the input capacitance of the cmos inverter is considered, cin equal to cgs,nmos+ cgd,nmos+ cgs,pmos,+cgd,pmos and cout= cdb,nmos+csb,nmos+cdb,pmos+csb,pmos + the input capacitace of next stage of inverter link.

    Is that right?

    From the results of the simulator, cgs is not equal to csg. Both of this two values is negative. Should I just ignore the negative sign and which value I should choose?

    Thanks! 

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  • IanX
    IanX over 11 years ago

    I have the same problems. I want to design a buffer chain. According to the design procedures from the book by Baker, I need to know the input capacitance of the inverter and the output capacitance of the inverter. What I try to do is do the DC analysis in cadence, then print the dc operating opoint. After that, we can see a lot of parameter listed in the table. 

    However, I felt a little confused. If the input capacitance of the cmos inverter is considered, cin equal to cgs,nmos+ cgd,nmos+ cgs,pmos,+cgd,pmos and cout= cdb,nmos+csb,nmos+cdb,pmos+csb,pmos + the input capacitace of next stage of inverter link.

    Is that right?

    From the results of the simulator, cgs is not equal to csg. Both of this two values is negative. Should I just ignore the negative sign and which value I should choose?

    Thanks! 

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