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Extraction of parasitic parameters of a MOS transistor used like switch

Ueue

Dear all,

I need to have a precise estimation of the parasitic capacitances of my MOSFETs, used as switches. I was thinking, for the measure of capacitances to impose a voltage source with voltage Vs increasing linearly with time and measuring the current (proportional to the capacitances). So Vs=K*t. For example connecting the generator to the gate, and the other terminals to ground, I could measure the Cgd and Cgs. Is it a good method?

Thanks a lot,

Stefano

Parents

  •  Dear IanX,

    I would approach your issue slightly differently. If you need to determine the input and output capacitances of an inverter, I would simulate the input and output capacitances directly as a function of inverter DC operating point and at a particular frequency. I have a test bench that I use quite frequently to determine the input impedance our output impedances of either devices or larger blocks (switches, buffers, etc.). The test bench applies an AC current to the device under test. A DC voltage is impressed to the device under test using a large inductor. The voltage across and current to the device are measured in an AC analysis, and at a particular frequency, the input reactance is computed to determine the input capacitance.  This method avoids the complexities of using BSIM model paramters to determine input and output capacitances of blocks. It also highlights the very significant impact of such things as Miller capacitance, parasitic routing capacitances (if used with the extracted view of a block). I hope this is useful to you.

     

    Shawn

     

Reply

  •  Dear IanX,

    I would approach your issue slightly differently. If you need to determine the input and output capacitances of an inverter, I would simulate the input and output capacitances directly as a function of inverter DC operating point and at a particular frequency. I have a test bench that I use quite frequently to determine the input impedance our output impedances of either devices or larger blocks (switches, buffers, etc.). The test bench applies an AC current to the device under test. A DC voltage is impressed to the device under test using a large inductor. The voltage across and current to the device are measured in an AC analysis, and at a particular frequency, the input reactance is computed to determine the input capacitance.  This method avoids the complexities of using BSIM model paramters to determine input and output capacitances of blocks. It also highlights the very significant impact of such things as Miller capacitance, parasitic routing capacitances (if used with the extracted view of a block). I hope this is useful to you.

     

    Shawn

     

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