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Problem in using AMS simulator in CADENCE Virtuoso ADE

ericliu
I am using CADENCE Virtuoso Analog Design Environment for simulation . The simulator opted is AMS. Basically, I have two main blocks to be simulated. One is written in verilog code and created as a functional view while the other block is drawn in schematic using foundry's cells. Thus, it is a mixed-signal simulation and AMS simulator is chosen.
When I simulated the config view of the above circuits, I got thousands of error messages (all in the same type) in my simulation.log
ncelab: *W,DLCILIB Library name 'primlib' not found, defaulting to 'PRIMLIB', please see nchelp on this error
PRIMLIB is a cell library provided by foundry. I reckon the simulator is trying to locate the lower case spelling, i.e., primlib, and couldn't find it. Someone on google suggest to modify the cds.lib file, for example,
DEFINE primlib $certain_directory/PRIMLIB
This will probably work. But does it mean that I have to change all the cells on my schematic from PRIMLIB to primlib. My design has probably 10 levels in the hierachy and hundreds of cells in it. Is there a better way to do it? The upper case spelling of PRIMLIB is the default thing, I do not incline to change it. 
  • I was told by an expert that an old way to solve this problem is to add the following line into .cshrc
    setenv CDS_ALT_NMP MATCH
    So the lower case and upper case spellings are no longer discriminated.
    But it is no longer supported. Anybody has an idea what the current solution is?
    Thanks

  • Best to contact customer support. I've only seen this kind of issue with VHDL libraries (if my memory is correct), and not with Verilog. You could tell AMS to ignore these warnings - there's an option to list the warning codes (DLCILIB in this case) that you want to filter. BTW, more info on this warning can be found by  typing "nchelp ncelab DLCILIB".

    Regards,

    Andrew,.

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