CIW > File > Import > Verilog... fails to create schematics (portOrder property?)

Hello

 I try importing the final verilog (.v) file generated by SoC encounter so I can do LVS for a mixed signal design, but ihdl.exe doesn't generate schematics. The beginning of the log file says (scgp is the digital library name in icfb):

@(#)$CDS: ihdl.exe version 5.1.0 12/16/2007 23:32 (cicln04) $ Fri Feb 5 15:20:53 2010

Compiling files:
1. /nfs/guille/moo/JAZZ_EXTENDED_LIBRARIES/verilog/src/scgp.v
into IR library SYNTHESIZED_STREAMIN_05
VerilogIn: *W,156: Rejecting lib 'scgp' cell 'nand3x1' view 'symbol' for module 'nand3x1' because terminal does not exist for a port in portOrder property.
VerilogIn: *W,31: Module nand3x1 in comparator not defined.Module comparator will be imported as functional.
VerilogIn: *W,31: Module nand3x1 in comparator not defined.Module comparator will be imported as functional.
VerilogIn: *W,156: Rejecting lib 'scgp' cell 'invx1' view 'symbol' for module 'invx1' because terminal does not exist for a port in portOrder property.
VerilogIn: *W,31: Module invx1 in comparator not defined.Module comparator will be imported as functional.
VerilogIn: *W,31: Module invx1 in comparator not defined.Module comparator will be imported as functional.
VerilogIn: *W,156: Rejecting lib 'scgp' cell 'nor2x2' view 'symbol' for module 'nor2x2' because terminal does not exist for a port in portOrder property.
VerilogIn: *W,31: Module nor2x2 in comparator not defined.Module comparator will be imported as functional.
VerilogIn: *W,31: Module nor2x2 in comparator not defined.Module comparator will be imported as functional.

and on and on. First I tried generating the final (.v) file from encounter with:

 saveNetlist -phys final.v -excludeCellInst {filler1 filler4}

but this made ihdl.exe complain about having the wrong number of pins, so I use:

  saveNetlist  final.v -excludeCellInst {filler1 filler4}

The (.gds) streams in perfectly. I can't find any documentation for ihdl.exe

Am I doing something wrong?

Skyler