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Cadence to Hierarchical PDF

Drwinco

I am trying to lend some help in reviewing a customer's design. They are providing bookmarked PDF output file from Cadence schematics however some of the hierarchy are RTL generated which makes for very dense drawings. The result is I lose the ability to read wire names, pin names and instance names in some of the higher level blocks. Is there any way to increase the resolution in a VIrtuoso schematic to PDF so as not to lose the pin/instance and wire name information? I understand that in the cdsplotinit file you can specify the dots per inch DPI resolution, page size etc for plotting and that this is then used in converting the .ps file to PDF. Also is there a tool that Cadence has that will allow traversable hierarchy in PDF or is that the bookmark scenario?

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  • Thanks for your reply. We already had the customer generate a PDF on 11X17 using the 6000 DPI but all we got was a mass of black lines and what may be instance symbols, rectangular boxes in the sea of black. Do you know if there are any additional parameters that need to be set on the Cadence side to insure readable text, pin names etc are generate? I assume that if you can zoom in and see the information on the Cadence side then it should appear in the postscript file and then the converted PDF? I seem to vaguely remember some issue regarding pixel size/resolution where certain text would not view when zooming in on a Cadence schematic. Also if we increase the resolution is there a limit and would a different paper size help, i.e larger such as D-size 22x34  or E? What we are dealing with are RTL generated schematics of logic blocks containing ~ 600+ logic gates, inverters, buffers, nor’s, nands, FF’s etc. Do you have any experience with this type of situation and do you foresee issues?  Also as another aside how does Cadence specify the paper size   :paperSize="B" 10500 16500 250 250: in other words can you translate the fields i.e. realtionship to 11x17 paper or is that a dumb question? Thanks again for your help.

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  • Thanks for your reply. We already had the customer generate a PDF on 11X17 using the 6000 DPI but all we got was a mass of black lines and what may be instance symbols, rectangular boxes in the sea of black. Do you know if there are any additional parameters that need to be set on the Cadence side to insure readable text, pin names etc are generate? I assume that if you can zoom in and see the information on the Cadence side then it should appear in the postscript file and then the converted PDF? I seem to vaguely remember some issue regarding pixel size/resolution where certain text would not view when zooming in on a Cadence schematic. Also if we increase the resolution is there a limit and would a different paper size help, i.e larger such as D-size 22x34  or E? What we are dealing with are RTL generated schematics of logic blocks containing ~ 600+ logic gates, inverters, buffers, nor’s, nands, FF’s etc. Do you have any experience with this type of situation and do you foresee issues?  Also as another aside how does Cadence specify the paper size   :paperSize="B" 10500 16500 250 250: in other words can you translate the fields i.e. realtionship to 11x17 paper or is that a dumb question? Thanks again for your help.

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