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Saving verilog-A variables in UltraSim

TonySal

I am trying to debug a verilog-A behavioral model, using UltraSim as my simulator.

How do I tell UltraSim to save the internal variables in my model, so I can view/plot them?

In Spectre there is an option saveahdlvars=all, but it does not seam to work in UltraSim.

  • Hi Tony

    Ultrasim does not have the equivalent of spectre's saveahdlvars. You can use the following instead:

    .probe all(I123)

    where I123 refers to the verilogA instance. The above cmd will save all signals and variables for instance I123. To save a particular variable or signal, you can use:

    .probe my_var_or_sig_name(I123)

    This is also explained in COS solution 11559680. : )

    Best regards
    Quek

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