Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 15096
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Problem with SepctreHDL and ahdl.def

riccart

Hi everyone,

Does anyone can help me to fix this problem.

I am trying to simulate my A2D and I am using the verilog file ''dac_10bit_ideal'' and ''sah_ideal''  from library ''ahdlLib'', but I have this Error.

FATAL (VACOMP-2095): File 'ahdl.def' does not appear to be a valid

Verilog-A file. In previous releases, 'ahdl.def' was a typical file name
for the SpectreHDL view of a component in the Virtuoso Analog Design Environment
but the software no longer supports SpectreHDL.

Thanks for your help !!
Parents
  • Thanks, but could you please explain me more.

    First of all, in attachment, you will see the set up of my design.
    I am using the symbol for bloc dac_10bit_ideal and sah_ideal. Of course, I took it from Library ahdlLib.
    In your response, you said that I have to use veriloga views instead of the views. But when I get a symbol, How can I know if this symbol was generated by the veriloga views or ahdl views.

    Here is the ahdl code for a sample and Hold

    // $Date: 1995/08/12 01:54:14 $
    // $Revision: 1.8 $
    //
    // The sample SpectreHDL library is unsupported and subject to change
    // without notice. Future versions of SpectreHDL may not be compatible
    // with this library.

    //--------------------------------------------
    // sah_ideal
    //
    //- ideal sample and hold amplifier
    //
    // vin:        [V,A]
    // vclk:    [V,A]
    // vout:    [V,A]
    //
    // INSTANCE parameters
    //    vtrans_clk = transition voltage of the clock [V]
    //
    // MODEL parameters
    // (none)

    module sah_ideal(vin, vout, vclk) (vtrans_clk)
    node [V,I] vin, vout, vclk;
    parameter real vtrans_clk=2.5;
    {
    real vout_val = 0 ;
       
        analog{
            if ($threshold(V(vclk) - vtrans_clk, 1.0))
                vout_val = V(vin) ;
                V(vout) <- vout_val ;
               }
    }          


    Here is the veriloga for a sample and Hold

    include "discipline.h"
    include "constants.h"

    // $Date: 1997/08/28 05:54:39 $
    // $Revision: 1.1 $
    //
    //
    // Based on the OVI Verilog-A Language Reference Manuel, version 1.0 1996
    //
    //


    //--------------------------------------------
    // sah_ideal
    //
    //- ideal sample and hold amplifier
    //
    // vin:        [V,A]
    // vclk:    [V,A]
    // vout:    [V,A]
    //
    // INSTANCE parameters
    //    vtrans_clk = transition voltage of the clock [V]
    //
    // MODEL parameters
    // (none)

    module sah_ideal(vin, vout, vclk);
    input vin,vclk;
    output vout;
    electrical vin, vout, vclk;
    parameter real vtrans_clk=2.5;
    real vout_val;
       
        analog begin
            @ (cross(V(vclk) - vtrans_clk, 1.0))
                vout_val = V(vin) ;
                V(vout) <+ vout_val ;
        end
             
    endmodule  

    Both come from ahdlLib.

    P.S. I'm a new on Cadence.

    Thanks again.
Reply
  • Thanks, but could you please explain me more.

    First of all, in attachment, you will see the set up of my design.
    I am using the symbol for bloc dac_10bit_ideal and sah_ideal. Of course, I took it from Library ahdlLib.
    In your response, you said that I have to use veriloga views instead of the views. But when I get a symbol, How can I know if this symbol was generated by the veriloga views or ahdl views.

    Here is the ahdl code for a sample and Hold

    // $Date: 1995/08/12 01:54:14 $
    // $Revision: 1.8 $
    //
    // The sample SpectreHDL library is unsupported and subject to change
    // without notice. Future versions of SpectreHDL may not be compatible
    // with this library.

    //--------------------------------------------
    // sah_ideal
    //
    //- ideal sample and hold amplifier
    //
    // vin:        [V,A]
    // vclk:    [V,A]
    // vout:    [V,A]
    //
    // INSTANCE parameters
    //    vtrans_clk = transition voltage of the clock [V]
    //
    // MODEL parameters
    // (none)

    module sah_ideal(vin, vout, vclk) (vtrans_clk)
    node [V,I] vin, vout, vclk;
    parameter real vtrans_clk=2.5;
    {
    real vout_val = 0 ;
       
        analog{
            if ($threshold(V(vclk) - vtrans_clk, 1.0))
                vout_val = V(vin) ;
                V(vout) <- vout_val ;
               }
    }          


    Here is the veriloga for a sample and Hold

    include "discipline.h"
    include "constants.h"

    // $Date: 1997/08/28 05:54:39 $
    // $Revision: 1.1 $
    //
    //
    // Based on the OVI Verilog-A Language Reference Manuel, version 1.0 1996
    //
    //


    //--------------------------------------------
    // sah_ideal
    //
    //- ideal sample and hold amplifier
    //
    // vin:        [V,A]
    // vclk:    [V,A]
    // vout:    [V,A]
    //
    // INSTANCE parameters
    //    vtrans_clk = transition voltage of the clock [V]
    //
    // MODEL parameters
    // (none)

    module sah_ideal(vin, vout, vclk);
    input vin,vclk;
    output vout;
    electrical vin, vout, vclk;
    parameter real vtrans_clk=2.5;
    real vout_val;
       
        analog begin
            @ (cross(V(vclk) - vtrans_clk, 1.0))
                vout_val = V(vin) ;
                V(vout) <+ vout_val ;
        end
             
    endmodule  

    Both come from ahdlLib.

    P.S. I'm a new on Cadence.

    Thanks again.
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.