Problem with SepctreHDL and ahdl.def

It sounds as if you could do with some basic training, or at least read some of the documentation.

Each cell has (potentially) multiple views. For example, a cell might have a symbol, a schematic, a veriloga, an ahdl view, a layout view, etc, etc. When you netlist for simulation, it needs to pick a particular view to simulate from each cell it finds in your design hierarchy. It's not a matter of the symbol being generated by the veriloga or ahdl view.

Netlisters in the Cadence IC tools work by a concept called "view switching". When it finds an instance of a symbol in your design, it will then descend the hierarchy by switching into another view alongside the symbol. In a pure schematic based design, this is controlled in ADE by the Switch List and Stop List on the Setup->Environment form in the Analog Design Environment. This might be something like:

Switch View List:  spectre cmos_sch cmos.sch schematic veriloga
Stop View List: spectre

The idea is that it tries each of the views in the switch list in turn, and if that view exists for a particular cell, it will switch into it and use it. Having switched into it, it then checks to see if that view was in the stop list, in which case it stops expanding the hierarchy during netlisting.

Maybe you have "ahdl" in your switch view list, and have it listed before veriloga? If you remove ahdl (and ensure that veriloga is there), or even just put veriloga before ahdl, it would pick up the veriloga view in preference to the ahdl view for simulation.

If instead of a simple schematic based design, you're using the hierarchy editor to create a config view, and are then simulating with that, you have finer control over which views are picked for which blocks. However, I doubt you can be doing that, because otherwise I would have been very surprised that you would have asked this question - you can't really use the hierarchy editor unless you understand the basics of simulating with different views.

Regards,

Andrew.

It sounds as if you could do with some basic training, or at least read some of the documentation.

Each cell has (potentially) multiple views. For example, a cell might have a symbol, a schematic, a veriloga, an ahdl view, a layout view, etc, etc. When you netlist for simulation, it needs to pick a particular view to simulate from each cell it finds in your design hierarchy. It's not a matter of the symbol being generated by the veriloga or ahdl view.

Netlisters in the Cadence IC tools work by a concept called "view switching". When it finds an instance of a symbol in your design, it will then descend the hierarchy by switching into another view alongside the symbol. In a pure schematic based design, this is controlled in ADE by the Switch List and Stop List on the Setup->Environment form in the Analog Design Environment. This might be something like:

Switch View List:  spectre cmos_sch cmos.sch schematic veriloga
Stop View List: spectre

The idea is that it tries each of the views in the switch list in turn, and if that view exists for a particular cell, it will switch into it and use it. Having switched into it, it then checks to see if that view was in the stop list, in which case it stops expanding the hierarchy during netlisting.

Maybe you have "ahdl" in your switch view list, and have it listed before veriloga? If you remove ahdl (and ensure that veriloga is there), or even just put veriloga before ahdl, it would pick up the veriloga view in preference to the ahdl view for simulation.

If instead of a simple schematic based design, you're using the hierarchy editor to create a config view, and are then simulating with that, you have finer control over which views are picked for which blocks. However, I doubt you can be doing that, because otherwise I would have been very surprised that you would have asked this question - you can't really use the hierarchy editor unless you understand the basics of simulating with different views.

Regards,

Andrew.