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Using custom gain factor

FilippoGua
Hi, I need to simulate an analog IC 0.35u process with mosfet with different gain-factor KP choosed by me with spectre simulator . I think to use mos1 model instead of Bsim3v3. I create a new cellview for both PMOS and NMOS. Defining a different value for "model" parameter in CDF. And I add a new model file *.scs in Virtuoso analog enviroment. IV simulation goes fine but AC goes very bad cause. Spectre doesn't consider gate capacitor (Cox*W*L) but only overlap capacitance. How I can do for insert the correct value of gate capacitance. Do someone help me? I use Cadence 5141 HitKit 4.70 MMSIM6.2

  • Without seeing what you've done, it's very hard to help.

    Can you post the model files you've created? (please make sure you're not contravening anyone's proprietary information when you do this - for example, if this is anything to do with AMS's models, you cannot post it here).

    Regards,

    Andrew.

  • Here is the model file. I hidden the values from the foundry. In the CDF i use mymosp as value for model. inline subckt mymosp ( d g s b ) parameters w=1.0e-6 l=1.0e-6 nrd=0.0 nrs=0.0 ad=0.0 as=0.0 pd=0.0 ps=0.0 ng=1 // mymosp ( d g s b ) mosinsub w=w l=l nrd=nrd nrs=nrs ad=ad as=as pd=pd ps=ps m=ng model mosinsub mos1 type=p capmod=2.0000e+00 \ vto=-1.33 kp=285e-06 lambda=0.03 gamma=0 phi=0.6 \ u0=XXXXX \ cgdo=XXX cgso=XXXX cgbo=XXXXXX \ xpart=XXXXXXX\ xl=XXXXXX xw=XXXXXXXX \ af=XXXXXX kf=XXXXXXX ef=XXXXXXX \ rd=XXXXX rs=XXXXXX rsh=XXXXXXXX \ minr=XXXXX \ rdc=XXXXX rsc=XXXXXXXX \ ldif=XXXXXXXXX hdif=XXXXXXXX \ js=XXXXXXXX \ n=XXXXXXXXX \ dskip=XX tlev=X tlevc=X \ cj=XXXXXX cjsw=XXXXX \ fc=XXXXXXXX fcsw=XXXXXXX \ mj=XXXXXXX mjsw=XXXXXXXX \ pb=XXXXXXX pbsw=XXXXXXXXX xti=XXXXXXX ends mymosp

  • Little hard to read because of the line wrapping. However, I see there is no tox parameter in the model.

    I'd advise you to read the Virtuoso Simulator Components and Device Models Reference in <MMSIMinstDir>/doc/spectremod/spectremod.pdf - in particular the Common MOSFET Equations section. There is a section (under Parameters Common to Levels 1-3 Only) which describes consistency between kp,u0, and Cox. That's probably your problem... especially as at the end of that section it says:

    • If tox is not indicated in the Level-1 model, the intrinsic MOSFET gate capacitances are not calculated.

    Regards,

    Andrew.

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