VIRTUOSO GXL Auto-Place & Route problems

Hi,

I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e  Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate all the corresponding layout cells. I have a few queries regarding the Custom Digital Placer. (I am working with the GUI, not any commands)

1. How do I insert Filler and standard cell substrate contacts in the layout? I read the instructions in the documentation. When I created a custom Std Cell Sub contact, and put it in the layout file, I can't label it as substrate contact component because it is not in the schematic. When i make its put a corresponding gate in the schematic of the design, I get an error saying it should be of type STDCELL. I would appreciate a description of exactly where and how to place substrate contacts and filler cells.

2. In Placement planning, the GPPG pattern in rails option should give me overlaping vdd and gnd rails. It gives seperate rails. is it dependent on some of the row attributes? When I ask it to use 0 spacing between rows, it just gives adjoining gnd gnd and vdd vdd rails.

3. When I ran the auto placer without inserting filler cells, and putting well contacts in my individual standard-cells, the final placement had DRC errors. But they were only due to inadequately spaced nwells. I checked the log and the following errors showed up

*WARNING* Layer pwell does not have maskNumber and will be ignored
*WARNING* Layer nwell does not have maskNumber and will be ignored
*WARNING* Layer gwell does not have maskNumber and will be ignored

From what I could infer from the documentation, the tool uses maskNumbers to check for DRC violations. Is that correct? And how do I get rid of this errors? The cells are otherwise abuttable.

4I also have one query regarding the Chip-Assembly router . When I run the router and successfully complete routing, there are new DRC errors due to misplaced vias.

I am using TSMC02 tech file.
Please advise on how to go about resolving these problems. If your solutions are based on scripting or typing out commmands instead of using the GUI, please give links on how to do command driven generation of layouts. My project involves creating a script for automated place and route of custom designs anyway, so it would be helpful

Thanks,

Tarun