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  3. tran simulation shows bad result with nport, while AC is...

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tran simulation shows bad result with nport, while AC is ok

TobiasM
TobiasM over 15 years ago

 Hi there,

I've got a problem with the nport from analogLib.
First, I create a S-parameter file by the following spectre netlist. It is a simple low pass (lp_1K_1u) filter and two ports. The S-parameter file is created by the sp simulation.
Then I created a second schematic containing the lp filter and a nport, where I loaded the previously created S-parameter file into.
The following AC-analysis showed good result, while the transient analysis was very bad, as the amplitude and phase were wrong.
I've already read the Application Note for nports and the Solutions concerning nports, especially the solution: "AC and tran simulation results do not match for circuits containing an nport". I tried different setups for the nport (linear/spline interopolation, windowing / no windowing), but nothing helped.
I think, my start frequency in sp analysis should suffice to create a good DC point.

Did anyone experience similar porblems or has an idea what else I could do?

Regards,
Tobias

netlist1:

// Generated for: spectre
// Generated on: Jun  1 13:10:00 2010
// Design library name: mat5rt
// Design cell name: sim_cmp_discrete_veriloga_lp_1K_1u
// Design view name: schematic_createSP
simulator lang=spectre
global 0
include "/tools/rbpdk/lbc8/links/$TI_PDK_VERSION/spectre/lbc8_bosch.scs" section=nom

// Library name: mat5rt
// Cell name: cmp_discrete_veriloga_lp_1K_1u
// View name: schematic
subckt cmp_discrete_veriloga_lp_1K_1u Vdd Vss out
    C0 (out Vss) capacitor c=1u
    R0 (Vdd out) resistor r=1K
ends cmp_discrete_veriloga_lp_1K_1u
// End of subcircuit definition.

// Library name: mat5rt
// Cell name: sim_cmp_discrete_veriloga_lp_1K_1u
// View name: schematic_createSP
I2 (net4 0 net3) cmp_discrete_veriloga_lp_1K_1u
PORT0 (net4 0) port r=50 type=sine
PORT1 (net3 0) port r=50 type=sine
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1e-6 gmin=1e-12 rforce=1 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
sp sp ports=[PORT0 PORT1] start=1e-9 stop=1e9 dec=60 \
    file="~/win_exchange/tmp/lp_1K1u.s2p" datafmt=touchstone \
    datatype=realimag noisedata=no oppoint=screen annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub

netlist 2:

/ Generated for: spectre
// Generated on: Jun  1 13:51:31 2010
// Design library name: mat5rt
// Design cell name: sim_cmp_discrete_veriloga_lp_1K_1u
// Design view name: schematic_cmp_schem_nport
simulator lang=spectre
global 0
include "/tools/rbpdk/lbc8/links/$TI_PDK_VERSION/spectre/lbc8_bosch.scs" section=nom

// Library name: mat5rt
// Cell name: cmp_discrete_veriloga_lp_1K_1u
// View name: schematic
subckt cmp_discrete_veriloga_lp_1K_1u Vdd Vss out
    C0 (out Vss) capacitor c=1u
    R0 (Vdd out) resistor r=1K
ends cmp_discrete_veriloga_lp_1K_1u
// End of subcircuit definition.

// Library name: mat5rt
// Cell name: sim_cmp_discrete_veriloga_lp_1K_1u
// View name: schematic_cmp_schem_nport
NPORT0 ( net7 0 net3 0) nport interp=spline fmax=1e8 thermalnoise=no \
        usewindow=yes datafmt=touchstone \
        file="~/win_exchange/tmp/lp_1K1u.s2p" dcextrap=constant \
        passivity=no pabstol=1e-06
PORT3 (net3 0) port r=50 type=sine
PORT2 (net7 0) port r=50 type=sine delay=250u freq=10K ampl=1 mag=1
PORT0 (net9 0) port r=50 type=sine delay=250u freq=10K ampl=1 mag=1
PORT1 (net15 0) port r=50 type=sine
I2 (net9 0 net15) cmp_discrete_veriloga_lp_1K_1u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1e-6 gmin=1e-12 rforce=1 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
tran tran stop=1m errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" method=gear2only annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
ac ac start=1 stop=1e8 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub

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  • Andrew Beckett
    Andrew Beckett over 15 years ago

    Hi Tobias,

    If I set fmax to 1e7 then the transient results match. Note that you can omit all the other parameters - setting fmax is sufficient to get the results to match in this case (although the other parameters on the nport don't do any harm - I'd generally advise setting usewindow=yes as a good thing anyway). I didn't have a chance to investigate why. I would suggest that you log this as a service request via http://support.cadence.com so that we can debug this properly.

    Regards,

    Andrew.

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