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subciruit initiated top-level current probe

Kalimero

Hi -  I have a simulation issue that I've been unable to resolve. I am using: 

Spectre Circuit simulator Ver 6.2.1.207 - Cadence 5.0.0 - icfb.exe version 5.1.0

 What I'm trying to do is to probe a top-level branch current from within a Subckt (included as a spectre model library).

The subckt defines a bsource component. The bsource expression is a function of  current through component "V2" (vsource dc = 0) which is a analogLib component on the main circuit. 

The simulator interprets my probe i("V2:0") as current through a device that is internal to the subckt - hence it return an error everytime stating that I1.V2 is not found on the netlist. (I1 is the instance name of the sunckt-defined component). 

this problem does NOT exist when I use a voltage probe and specify any external nets.

I can get around this problem if I fake a ligitimate path for the current probe. For example if  I make it a function of current through a component that resides within a bogus subckt I have created and included in the circuit. i.e. i("I3.V2:0") works just fine ( I3 is the instance name of my bogus subcircuit componenet and V2 is a zero volt dc source within it. How can I do the same for a standalone analogLib component on the main circuit ... I would be grateful for any feedback. - thanks you    

  • I'm afraid your question is not that clear to me. Where are you specifying this "probe"? Perhaps some example data might be a good idea to illustrate this (even some pictures and netlists)?

    That said, having read through a few times, I've guessed you might be describing something like this:

    //

subckt subthing (a b)
R1 (a b) bsource r=1k*i("V2:0") 
ends subthing

subckt subsrc (a b)
V2 (a b) vsource dc=1
ends subsrc

V2 (x 0) vsource dc=1
//I3 (y 0) subsrc dc=1
R1 (y 0) resistor r=100
V1 (x 0) vsource dc=1
R2 (x 0) subthing

dc dc
stuff info what=oppoint where=screen

    If so, you're saying that when you have V2 referenced in the subthing subckt, it fails with an error:

    Error found by spectre during initial setup.
        ERROR (VLOGA-5034): "Internal (bsource)" 0: R2.R1(bsource/B-element):
            Probe `R2.V2' does not exist in the netlist. Fix the problem and try
            again.
     

    but if you did this:

    //

subckt subthing (a b)
R1 (a b) bsource r=1k*i("I3.V2:0") 
ends subthing

subckt subsrc (a b)
V2 (a b) vsource dc=1
ends subsrc

//V2 (x 0) vsource dc=1
I3 (y 0) subsrc dc=1
R1 (y 0) resistor r=100
V1 (x 0) vsource dc=1
R2 (x 0) subthing

dc dc
stuff info what=oppoint where=screen

    then it works? Is that it? I can see why - a "relative" path in an expression in a bsource is assumed to be within the subckt (which is quite handy, in fact) - but in this case you want it to resolve to the top level.

    Regards,

    Andrew.

  • I apologize for the lack clarity in my initial question. Thank you for your answer Andrew. What you described is precisely the problem I am having. After looking through the manual, my understanding was that in spectre, unlike ultrasim, signal path specified in an expression starts at the top-level by default. If a signal path in a bsource -based expression is defined relative to the associated subckt, then how do I specify a path to the main circuit?. I have tried using the <top cell name.V2:0>, <0.V2:0> and several other identifiers, but nothing works. Is there a way to specify a path to a top level component from inside the bsource subckt ?...        

  • The reason I'm asking is because in Virtuoso Spectre, the netlist is automatically generated from the schematic and so the use of bsource requires one to add a bsource component to the schematic and define the bsource expression in a subckt. As such, in the event that the bsource expression is a function of the current through a top-level components, access to this current must be specified through a path from within the subcket. . If there is no way to specify a path directly to a top-level branch, then as I had stated this can be rigged by adding a bogus symbol that contains a zero volt Vdc to the schematic at the point one wished to probe. Then a valid path for the current probe to the main circuit can be provided in the bsource expression. I just want to make sure this is the only way to go about this as I have to tutor several of my colleagues on the use of bsource and I'm trying to avoid disseminating work-around solutions if possible.

  • I'm not aware of any solution other than the workaround you've found.

    I plan to raise a CCR with R&D on this, as it ought to be possible to specify a top level source in the expression (maybe by putting ".V2:0" - although that doesn't work at the moment)

    Regards,

    Andrew.

  •  Thank you Andrew, i(".V2:0") does sound like the most logical identifier for a top-level signal - The workaround is simple enough, I was just under the burden of verifying the information before passing it on. I am grateful for your help.  

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