• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. assura lvs problem in ibm 90nm pdk

Stats

  • Locked Locked
  • Replies 21
  • Subscribers 126
  • Views 22015
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

assura lvs problem in ibm 90nm pdk

iamlearning
iamlearning over 15 years ago
Hi all,
Inspite of 'check and save'ing my schematic from the schematic window and recreating the cdl netlist several times, I am getting the following error when doing the LVS of a mimcap of ibm 90nm process with assura32-cadence ic613.

Loading IBM PDK cms9flp Procedures for Cadence Version

"av3.2:Production:dfII6.1.3:IC6.1.3.500.4"
Net Listing Mode is Analog
*Error* schematic cell: rf9flp mimcap symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
1 error(s) encountered, vldb not generated
Error - dfIIToVldb failed to execute

*WARNING* /usr/local/cadence/assura32/tools/assura/bin/nvn exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated


This problem is only for the cells containg mimcap and iductor, because I could complete the lvs of an inverter successfully. Even, this error does not apear when I use assura317 instead of assura32.

Can anyone please give me any clue to get out of this strange error?
Thank You ...
  • Cancel
Parents
  • iamlearning
    iamlearning over 15 years ago

    Thank you Quek for your keen observation. I have uploaded newer files in http://www.4shared.com/file/vbM3bfOl/lvs_errors3.html . My log files with assura317 are not latest, as can be seen there if the simulation dates are checked, because I can no longer complete the lvs with either version of assura. So, I picked the complete lvs log files from my previous records. The recent log files are same for both the versions.

    Both the log files notes the names of the Layout and schematic cells, which is 'caps' everywhere.

    One more observation is, the following warning comes twice in lvs_Errors_av32.log and once in lvs_Errors_av317.log, though I dont know whether it speaks something here.

    *WARNING* The capability to discard or ignore devices is not available
                       Therefore all devices were included in the output
                       Even though no *.BIPOLAR command was found

    Would you please try to dig something out of here?

    Thank You Very Much...
    Regards

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • iamlearning
    iamlearning over 15 years ago

    Thank you Quek for your keen observation. I have uploaded newer files in http://www.4shared.com/file/vbM3bfOl/lvs_errors3.html . My log files with assura317 are not latest, as can be seen there if the simulation dates are checked, because I can no longer complete the lvs with either version of assura. So, I picked the complete lvs log files from my previous records. The recent log files are same for both the versions.

    Both the log files notes the names of the Layout and schematic cells, which is 'caps' everywhere.

    One more observation is, the following warning comes twice in lvs_Errors_av32.log and once in lvs_Errors_av317.log, though I dont know whether it speaks something here.

    *WARNING* The capability to discard or ignore devices is not available
                       Therefore all devices were included in the output
                       Even though no *.BIPOLAR command was found

    Would you please try to dig something out of here?

    Thank You Very Much...
    Regards

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information