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assura lvs problem in ibm 90nm pdk

iamlearning
Hi all,
Inspite of 'check and save'ing my schematic from the schematic window and recreating the cdl netlist several times, I am getting the following error when doing the LVS of a mimcap of ibm 90nm process with assura32-cadence ic613.

Loading IBM PDK cms9flp Procedures for Cadence Version

"av3.2:Production:dfII6.1.3:IC6.1.3.500.4"
Net Listing Mode is Analog
*Error* schematic cell: rf9flp mimcap symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
1 error(s) encountered, vldb not generated
Error - dfIIToVldb failed to execute

*WARNING* /usr/local/cadence/assura32/tools/assura/bin/nvn exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated

This problem is only for the cells containg mimcap and iductor, because I could complete the lvs of an inverter successfully. Even, this error does not apear when I use assura317 instead of assura32.

Can anyone please give me any clue to get out of this strange error?
Thank You ...
Parents
  • iamlearning

    Sorry for the delayed Feedback. "view list" and "stop list" of the "Netlisting Options" are "auLvs schematic symbol" and "auLvs" respectively and there is no "auLvs" view for the mimcap and inductor cells, olnly shcematic, layout, symbol and auCdl views. So, may be you knocked right :) . I also noticed that, there is "auLvs" view for the 'nfet', but not for 'nfet_rf'. Still, I could complete the LVS of an inverter consisting of 'nfet_rf'. Moreover, lvs of the mimcap and inductor can be performed by assura317 with the same "view list" and "stop list" in the "Netlisting Options"  and with no "auLvs" view of them.

    Would you please write me what can I do in this situation? Thank you for your tips :)

    Regards ..

Reply
  • iamlearning

    Sorry for the delayed Feedback. "view list" and "stop list" of the "Netlisting Options" are "auLvs schematic symbol" and "auLvs" respectively and there is no "auLvs" view for the mimcap and inductor cells, olnly shcematic, layout, symbol and auCdl views. So, may be you knocked right :) . I also noticed that, there is "auLvs" view for the 'nfet', but not for 'nfet_rf'. Still, I could complete the LVS of an inverter consisting of 'nfet_rf'. Moreover, lvs of the mimcap and inductor can be performed by assura317 with the same "view list" and "stop list" in the "Netlisting Options"  and with no "auLvs" view of them.

    Would you please write me what can I do in this situation? Thank you for your tips :)

    Regards ..

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