Stats

  • Locked Locked
  • Replies 9
  • Subscribers 124
  • Views 8970
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cadence 6 waveform error vpwl vsrc

StreamCX

When I add vpulse or vpwl source to schematics, this message appears:

[img]img44.imageshack.us/.../img]

are given"

 

And another problem

When i add vpwl (name V5) signal with params like

 0s, 0 V

14us, 0 V

30us 5V

error appears

 "Netlist error: missing parametr V2 in V5"

 "Netlist error: missing parametr V1 in V5" 

Parents

  • That too looks like a lack of CDS_Netlisting_Mode being set.

    I've no idea what the second is. You didn't say how you set up the source. Where are you adding the "vpwl (name V5) signal". 

    Please try to take care to carefully describe the problem with all the relevant information. Debugging from the above is virtually impossible...

    Regards,

    Andrew.

Reply

  • That too looks like a lack of CDS_Netlisting_Mode being set.

    I've no idea what the second is. You didn't say how you set up the source. Where are you adding the "vpwl (name V5) signal". 

    Please try to take care to carefully describe the problem with all the relevant information. Debugging from the above is virtually impossible...

    Regards,

    Andrew.

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.