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import verilog

eppo
Hi, I use the TSMC 65nm Design-Kit and I have a problem when I want to import a file in verilog. In fact, I get the following error: ncvlog: *W,DLNOHV: Unable to find an 'hdl.var' file to load in. Also, in reference libraries it does not recognize the sample library. I have a message telling me that : ' Library (sample) not initialised in the database. Is someone can help me? Regards, M.A. Bounouar
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  •  Hi,

    Do you need to run the post-install configuration for your tool installation?  InstallScape has a "Configure" button. The Verilog and VHDL files that come with the installation need some configuration before use.

    Regards,

    Lawrence.

Reply

  •  Hi,

    Do you need to run the post-install configuration for your tool installation?  InstallScape has a "Configure" button. The Verilog and VHDL files that come with the installation need some configuration before use.

    Regards,

    Lawrence.

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