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Interconnect capacitance

Ueue

Dear all,

I have to design a circuit in which there are some capacitances that have to be resistent to high voltages. These capacitances are not available in the technology library, but I could realize them through the use of capacitances between different metal layers. So, during the design, I was planning to use ideal capacitances. The problem is how to execute the LVS of this circuit. In general, I don't know what is the proper way for designing a cell in which there will be components designed by myself and not contained in the technology library.

Let me know.

Thanks a lot,

Stefano

  • Hi Stefano

    At the very minimum, I think you can blackbox both layout and schematic cap cell for lvs if it is really too difficult to write the device extraction rules for the special capacitor which you have to design. : )  Hope that I am understanding your question correctly.

    In general, the following preparations are necessary for lvs of a custom device:
    a. Write device extraction rules for the lvs tool
    b. Write the necessary compare cmds to check the various parameters
    c. Create a schematic/cdl representation of the device

    Best regards
    Quek

  • Hi Quek,

    I think that it a very good solution.

    Thanks,

    Stefano

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