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amsdesigner with Systemverilog

Hallo,

We are wanting to use a Sytemverilog written testbench to stimulate and check the mixed signal simulation using amsdesigner.

I seem to remember reading that amsdesigner doesn't recognise all Systemverilog constructs. Am I remebering this correctly, as I can't find any reference in the amsdesigner user guide, just information on port and wire bindings.

Many thanks

Adam

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