Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 14024
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

NCSU CDK 1.6, IC v6.1.4, and ADE simulation?

elbUtah
Hi - I'm trying to get things working with IC v6.1.4 and the NCSU CDK 1.6. I've managed to get basic things working up through simple schematics and layout. But, I'm getting stuck trying to simulate a schematic that has nmos and pmos components from the NCSU_Analog_Parts library using ADE and Spectre. ADE croaks when trying to create the netlist with the error: ERROR (OSSHNL-371): Netlisting failed because the terminal 'bn' was not found on the instance 'M2' in cellview 'trythis/nand2/schematic'. Provide correct terminals on the instance by referring to its switched master and netlist again. The netlisting environment has a switch view list of "spectre cmos_sch cmos.sch schematic veriloga" and a stop view list of "spectre", the nmos and pmos cells do have terminals named bn. These are the cdb2oa-translated cells that come with the NCSU CDK 1.6. The bn terminal on the spectre view of the nmos device (for example) has the following properties: Name = bn, Property Name = inh_bn, Default Net = gnd!, Evaluated Name = gnd!, Direction = InputOutput. This is just like the old ICv5.1.41 cell. This all worked fine in IC v5.1.41. Is there some change to the way the netlisting procedure evaluates bn nodes in v6.1.4 that could cause this error? Has anyone gotten analog simulation with spectre/ADE, the NCSU CDK, and IC v6.1.4 working? Any help would be greatly appreciated! Thanks, -Erik

  • Wouldn't it make more sense to ask NCSU about this?

    Andrew.

  • You're right, of course. I also posted this question to the NCSU forum at chiptalk.org, but I thought someone reading this forum might have already wrestled with this problem, and that it might be a difference in the way v5.1.41 and v6.1.4 did netlisting rather than a specific NCSU issue. As so often happens, after hours of beating my head against the wall, I finally post a query, and then an hour later I figure it out... If I could just figure out when this is going to happen I could avoid bothering people with posting! :-) The issue is with a variable that controls how netlisting treats "switch masters" during netlisting. When NC_Verilog netlists a circuit from composer, it reports in an info that "it is recommended to set the terminal SyncUp option on the NetlistSetup form as 'Honor Switch Master'" and recommends setting the hnlVerilogTermSyncUp variable to 'honorSM'. So, innocently, I did this, thinking that it would only have an impact on nc_Verilog netlisting. It works fine for NC_Verilog netlisting, but messes up spectre netlisting for ADE. Digging deeper there's a line buried in the documentation that the honorSM option does not work for "explicit netlisting" so I assume that explicit netlisting is what is done for ADE (even though Verilog is not directly involved since it's netlisting to a spectre netlist). The short version of the answer is - make sure the hnlVerilogTermSyncUp variable is NOT set to 'honorSM'. You'll have to put up with the info message from NC_Verilog, but don't take its advice! -Erik

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.