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LVS errors

tester

Hi All,

I am using ic5.1.41 for schematic, Virtuoso XL layout and Jazz CA 18 for design kits. After running LVS, I got the following warning and error message. Can anyone give me some hints please? thanks

 

  • Quek

    Hi tester

    Would you please upload your cls file? This means the file with .cls extension in the run directory. It would be great if you can also provide the specific version of the tool which you are using. E.g.

    terminal>assura -W

    Thanks
    Quek

  • tester

    Dear Quek,

    Thank you very much for your email. Here is the information that you requested:

    assura -w gives:

    ********************************************************************* 

    Assura (tm) Physical Verification Version av3.2:Production:dfII5.1.41:5.10.41.500.6.130

    Release 3.2_USR2_HF7

    no mcf file specified

    ***********************************************************************

    The following is the attached cls file

     

    test2.doc
  • Quek

    Hi tester

    It looks like rppoly_lo and ind devices in your layout cannot be extracted. This should be the main cause of your net mismatches. An in- depth troubleshooting would be required to understand why the devices cannot be extracted. Possible reasons are:

    a. Bug in extract.rul file
    b. Pdk and extract.rul file are out of sync. Pdk devices now uses slightly different layers and hence are not recognized by the rule deck

    Please contact your local Cadence support for more help. : )

    Best regards
    Quek

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