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LVS error concerning multiplicity of transistors + IBM cms9flp

jimito13

Hello everyone,

I came up with the following LVS error concerning all transistors with multiplicity factor m (NOT with just fingers and no multiplicity factor in contrary) in my design.LVS debug environment details give the following description :

FET1comp has mismatched parameter(s):"w" layout: 1.5e-05 schematic: 7.5e-06

Let me be more specific.For the above description,in my design i have a transistor with Wtotal=15um and multiplicity factor m=2 (thus 2 fets in parallel with 7.5um width each),well,assura can make the correct computation for the layout and it shows the actual Wtotal but it cannot estimate the correct value for the Wtotal for the side of the schematic (it seems considering m=1 always independent from the value i have set in the fet properties).Is there any way to get rid of this error (with some switch under Modify avParameters menu for example) or i should make any change to the compare rules file to the respective funtion?I show you the properties of the nfet :

Width Single Finger : 7.5u
Width All Fingers :7.5u
Fingers :1
Multiplicity :2

Thus,Wtotal=15u as i mentioned earlier.

The following lines contain the part of the compare.vldb file with the respective section for the FET1comp function :

procedure( FET1comp(m1, m2)
let((paraminfolist )
paraminfolist='(
("l" "abs_comp" "if(BentGate<0.5 then hgp else hgp7)")
("w" "abs_comp" "if(BentGate<0.5 then hgp else hgp7)")
)
unless(getValCase(m1 "m") m1->m=1)
unless(getValCase(m2 "m") m2->m=1)
unless(getValCase(m1 "idg") m1->idg=0)
unless(getValCase(m2 "idg") m2->idg=0)
if( (m1->idg && abs_comp(m1->idg 0 0.5)) then
m1->w = getValCase(m1 "w") * getValCase(m1 "m") )
if( (m2->idg && abs_comp(m2->idg 0 0.5)) then
m2->w = getValCase(m2 "w") * getValCase(m2 "m") )
unless(getValCase(m1 "bentgate") m1->bentgate=0)
unless(getValCase(m2 "bentgate") m2->bentgate=0)
BentGate = m1->bentgate + m2->bentgate
genericcomp("FET1comp" m1 m2 paraminfolist)
)
) 

I must say that i use IBM cms9flp pdk finally if somebody didn't notice that on the post subject.Also Cadence IC 6.1.3 under opensuse 11.1 operating system 64-bit.

Can somebody give me a helpful hint how to solve this problem?Changing all transistor to bus will be a painful procedure for me and i want to avoid it if possible.

Thanks in advance for any helpful answer and if more clues are needed ask me to post them here.

  • Hi / Yiassou,

    If you have an approaching deadline, wouldn't it be a good idea to
    create a Service Request with customer support?

    Good luck!
    Lawrence.

  • Hi Yiassou

    Just as what Lawrence has suggested, I think it would be good if you can file a service request to your local Cadence support. If your pcell does not have the MULTI DEV layer even after setting multiplicity parameter to be greater than 1, then it seems to be a pcell problem. Would it be possible to resolve the problem by manually creating a MULTI DEV layer over the appropriate pcells?

    Best regards
    Quek

  • Hello guys,

    Thanks for your interest and your replies :-) Can you please guide me to set up the MULTI DEV layer?From where it should be present normally,from the cadence virtuoso XL/assura GUI or from a file?If possible show me a part of a correct file if it must be configured from there.And a final question,what we mean saying "pcell"?

     Thanks in advance for any hepful suggest.

    Best Regards,

    Jimito13

  • Hi Jimito

    Pcell refers to "parametrized" cells. This means that the cell layout can change according to the changes made in the properties form. The cells in your IBM pdk are pcells which you can used in your layout. Please go to LSW, set all layers as valid and check if there is a layer named "multidev" (my guess). : )   Create a rectangle that covers your cell using this layer. Now re-run lvs to see if it makes a difference.

    I would also strongly suggest that you contact Cadence support now to get more help on troubleshooting this.

    Best regards
    Quek

  • Hello Quek,

    I have already searched for this layer but i can't find it and i have already mentioned it in previous e-mail to IBM's support,but they didn't give any feedback except from admitting that there is a bug in VLDB mode LVS...The main problem is that i am not talking myself directly with IBM and my professor that does this insists that i must do the following : wherever in schematic i have devices with m factor to substitute them with m parallel single devices in order to pass LVS.But this is going to cost a lot of time i think.Anyway,i will see how to deal with this.Thanks again for your precious help.

     Best Regards,

    Jimito13

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