LVS error concerning multiplicity of transistors + IBM cms9flp

Hi jimito

This indeed seems like a small bug in the compare rules. IBM pdks have long compare rules file and so I think ultimately you might have to request for more support from your local IBM or Cadence support centre.

Would you please check the cdf info for the cell to see if the multiplicity property is really "m" or some other name (e.g. mfac, mf, etc)?

In ciw, go to "Tools->CDF->Edit CDF".

Thanks
Quek

 I checked the menu you suggested but i didn't find any information...

Hi jimito

Suppose the multiplicity problem is for a schematic cell named "nfet123" in library "myTechLib". Would you please help to execute the following cmd in ciw and upload the output file "cell.cdf"? Please use the upload function, not cut and paste.

cdfDump("myTechLib" "cell.cdf" ?cellName "nfet123" ?level 'base)

Please also provide the following info:
terminal>assura -W
terminal>virtuoso -W

Please also upload the "design.vlr" file in the lvs run directory.

Thanks
Quek

 Hello Quek,

 At first thanks for your interest to my problem.I run the command in ciw but the cell.cdf output file is empty(!),so there is no reason to upload.What can we see from this file if it had something in it?

 The file with .vlr extension is IBM confidential and i can't post it or upload it anywhere...Guide me with a similar file that apparently you have as well and i will give you the feedback for the thing that we must know from that file.

 Output from the 2 commands in terminal :

 IC6.1.3.500.13

3.2_USR2_HF11

Regards

Hi jimito

I am trying to find out the actual cdf parameter name for the "multiplicity" parameter in the properties form. Not very sure why your cdfDump is empty. : )  Would you please help to do the following?

a. In the ciw (this is the first window that shows up when Virtuoso starts up), go to "Tools->CDF->Edit CDF"
b. Use the "Browse" button and select the transistor that has the problem.
c. The cdf form shows up
d. In the top right hand corner, enter a filename and press the "CDF dump"

Hopefully the gui will be able to help you generate a proper file. Please upload the file.

Thanks
Quek

Quek,

I did the procedure you mentioned above but at first i am not given the ability from the gui to choose the transistor that has the problem but i can choose the schematic or layout view,so doing this the cell.cdf file has some parameters with "nil".Doing what you suggested for a single nfet of the cms9flp library,the actual cdf parameter name for the "multiplicity" parameter is "m".What is exactly the CDF??

 And a final and a little bit irrelevant question with the above.Virtuoso makes sometimes a sound like a beep.I know how to shut it down,but i want to do it permanently...Do you know a command that i can write in a file (is this file .cdsinit?) to do it?

 Thanks in advance.

jimito13 said:

And a final and a little bit irrelevant question with the above.Virtuoso makes sometimes a sound like a beep.I know how to shut it down,but i want to do it permanently...Do you know a command that i can write in a file (is this file .cdsinit?) to do it?

I do this in .cdsenv, but you can easily change the syntax if you want it to be in .cdsinit:

ui beepVolume int -100
 

Hi jimito

CDF refers to Component Description Format. It contains the parameter that your instances has and controls which parameters go into the netlist. Since "multiplicity" does indeed has parameter name "m", it is not a matter of indentifying a custom mfactor name to Assura. It would be quite tough to debug without a testcase so it would be good if you can contact your local Cadence/IBM support for this problem.

Best regards
Quek

Hello Quek,

Thank you very much for your effort to help me with this problem.This is the last step,to contact my IBM representative...Hope they have a solution.

Best Regards,

Jimito13

 Well,i contacted IBM and the first answer was this :

"In layout, if the pcell has multiplicity parameter set to >1, then there will be a layer called MULTI DEV surrounds the pcell. This will prevent the LVS from combining devices in the layout"

 I replied to them saying that i can't find that layer anywhere and asked them to guide me to find it and the final anwer was this :

"It appears that in cms9flp Assura VLDB mode LVS does have some problems recognizing multiplicity from the schematic side. Assura CDL mode and Calibre LVS will both recognize multiplicity properly. I will investigate further on the Assura VLDB mode LVS. Please use CDL mode LVS or Calibre LVS if you can"

The problem is the following,trying to use CDL the error vanishes but others concerning devices and nets come up that don't make sense since my testcase is one nfet so if there was such an error it could be visible easily.Other problem is that we don't have calibre and the time to learn how to use it until the tape-out that is in a few days!

Finally i decided that i must change to bus mode naming for the transistors and the problem is solved partially since some nets get strange name like net33<0> and i can't even check n' save my schematic...

I am in desperate condition,please if somebody knows a way to get rid of this damn problem,let him do it,i will appreciate it.

Thanks in advance.