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LVS error concerning multiplicity of transistors + IBM cms9flp

jimito13

Hello everyone,

I came up with the following LVS error concerning all transistors with multiplicity factor m (NOT with just fingers and no multiplicity factor in contrary) in my design.LVS debug environment details give the following description :

FET1comp has mismatched parameter(s):"w" layout: 1.5e-05 schematic: 7.5e-06

Let me be more specific.For the above description,in my design i have a transistor with Wtotal=15um and multiplicity factor m=2 (thus 2 fets in parallel with 7.5um width each),well,assura can make the correct computation for the layout and it shows the actual Wtotal but it cannot estimate the correct value for the Wtotal for the side of the schematic (it seems considering m=1 always independent from the value i have set in the fet properties).Is there any way to get rid of this error (with some switch under Modify avParameters menu for example) or i should make any change to the compare rules file to the respective funtion?I show you the properties of the nfet :

Width Single Finger : 7.5u
Width All Fingers :7.5u
Fingers :1
Multiplicity :2

Thus,Wtotal=15u as i mentioned earlier.

The following lines contain the part of the compare.vldb file with the respective section for the FET1comp function :

procedure( FET1comp(m1, m2)
let((paraminfolist )
paraminfolist='(
("l" "abs_comp" "if(BentGate<0.5 then hgp else hgp7)")
("w" "abs_comp" "if(BentGate<0.5 then hgp else hgp7)")
)
unless(getValCase(m1 "m") m1->m=1)
unless(getValCase(m2 "m") m2->m=1)
unless(getValCase(m1 "idg") m1->idg=0)
unless(getValCase(m2 "idg") m2->idg=0)
if( (m1->idg && abs_comp(m1->idg 0 0.5)) then
m1->w = getValCase(m1 "w") * getValCase(m1 "m") )
if( (m2->idg && abs_comp(m2->idg 0 0.5)) then
m2->w = getValCase(m2 "w") * getValCase(m2 "m") )
unless(getValCase(m1 "bentgate") m1->bentgate=0)
unless(getValCase(m2 "bentgate") m2->bentgate=0)
BentGate = m1->bentgate + m2->bentgate
genericcomp("FET1comp" m1 m2 paraminfolist)
)
) 

I must say that i use IBM cms9flp pdk finally if somebody didn't notice that on the post subject.Also Cadence IC 6.1.3 under opensuse 11.1 operating system 64-bit.

Can somebody give me a helpful hint how to solve this problem?Changing all transistor to bus will be a painful procedure for me and i want to avoid it if possible.

Thanks in advance for any helpful answer and if more clues are needed ask me to post them here.

Parents

  •  Well,i contacted IBM and the first answer was this :

    "In layout, if the pcell has multiplicity parameter set to >1, then there will be a layer called MULTI DEV surrounds the pcell. This will prevent the LVS from combining devices in the layout"

     I replied to them saying that i can't find that layer anywhere and asked them to guide me to find it and the final anwer was this :

    "It appears that in cms9flp Assura VLDB mode LVS does have some problems recognizing multiplicity from the schematic side. Assura CDL mode and Calibre LVS will both recognize multiplicity properly. I will investigate further on the Assura VLDB mode LVS. Please use CDL mode LVS or Calibre LVS if you can"

    The problem is the following,trying to use CDL the error vanishes but others concerning devices and nets come up that don't make sense since my testcase is one nfet so if there was such an error it could be visible easily.Other problem is that we don't have calibre and the time to learn how to use it until the tape-out that is in a few days!

    Finally i decided that i must change to bus mode naming for the transistors and the problem is solved partially since some nets get strange name like net33<0> and i can't even check n' save my schematic...

    I am in desperate condition,please if somebody knows a way to get rid of this damn problem,let him do it,i will appreciate it.

    Thanks in advance.

     

Reply

  •  Well,i contacted IBM and the first answer was this :

    "In layout, if the pcell has multiplicity parameter set to >1, then there will be a layer called MULTI DEV surrounds the pcell. This will prevent the LVS from combining devices in the layout"

     I replied to them saying that i can't find that layer anywhere and asked them to guide me to find it and the final anwer was this :

    "It appears that in cms9flp Assura VLDB mode LVS does have some problems recognizing multiplicity from the schematic side. Assura CDL mode and Calibre LVS will both recognize multiplicity properly. I will investigate further on the Assura VLDB mode LVS. Please use CDL mode LVS or Calibre LVS if you can"

    The problem is the following,trying to use CDL the error vanishes but others concerning devices and nets come up that don't make sense since my testcase is one nfet so if there was such an error it could be visible easily.Other problem is that we don't have calibre and the time to learn how to use it until the tape-out that is in a few days!

    Finally i decided that i must change to bus mode naming for the transistors and the problem is solved partially since some nets get strange name like net33<0> and i can't even check n' save my schematic...

    I am in desperate condition,please if somebody knows a way to get rid of this damn problem,let him do it,i will appreciate it.

    Thanks in advance.

     

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