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Unable to export CDL file

Renee

Hi, 

I tried to export a cdl file from a small cell sw_dummy(it contains only basic MOS transistors), although it succeeded, the netlist was empty.

Then I tried to export the cdl from Calibre LVS function, but it failed. The error I get is: Netlister: unable to descend into any of the views defined in the view liste: "Cdl schematic" for instance M0 in Cell sw_dummy.

But the circuit designer can export cdl files successfully.

Then, I checked the si.env files, and I think I might find the problem:

In my si.env file, it defines:

 simViewList=`("cdl" "schematic") simStopList=‘（"cdl"） simSimulator='("cdl")

But in the ckt designer's si.env file, it defines:

 simViewList=`("auCdl" "schematic") simStopList=‘（"auCdl"） simSimulator='("auCdl")

I tried to change cdl to auCdl, but later I found that the si.env file changed it back every time I exported the CDL file.

Is there any way I can solve this problem?

 Thanks in advance!

  • Before starting Virtuoso use:

    setenv CDS_Netlisting_Mode Analog

    Or if using bash or ksh:

    export CDS_Netlisting_Mode=Analog

    That should change the default CDL netlister to "auCdl". If using File->Export->CDL you get a choice of Analog or Digital on the form, but the Calibre interface may not give you that (not a Cadence tool,so I can't say).

    Regards,

    Andrew

  • Thank you very much for your reply!

    I already solved this problem with your method.

    Although I could set the Netlisting Mode directly to Analog in the form of exporting CDL file in cadence, then it worked, however it did not change the variable CDS_Netlisting_Mode, thus I failed to export the CDL file when I started Calibre LVS and tried to export that file there. It seems that the Calibre LVS exporting CDL file tool relies on the cadence platform to perform the netlisting job.

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