Have device connectivity added as an include?

It's just a large duplication of information that already exists elsewhere.

For example, a simple testbench for a simple circuit produces an input.scs of over 400 lines (see truncated example below).  Just imagine if this were a larger circuit and I was using extracted views. Jeesh!

--------------------------- First  Example - Existing input.scs---------------

// Generated for: spectre
// Generated on: Aug 13 15:02:09 2010
// Design library name: test
// Design cell name: tb_test_ckt
// Design view name: schematic
simulator lang=spectre
global 0
parameters start_vdc=0.6 supply_r=1.2 start_delay=1n enable_delay=1n \
    fin_time=1.5u
include "/import/foundry/foundry_geom/pdk/datecode/../models/spectre/toplevel.scs" section=top_tt

// Library name: test
// Cell name: test_ckt
// View name: schematic
subckt test_ckt enable_bar ibandgap vddr vref vssa
    MN0 (start1 n1 vssa vssa) nch_mac l=1.5e-07 w=9u multi=1 nf=9 \
        sd=120.0n ad=4.75e-13 as=4.75e-13 pd=10.950u ps=10.950u \
        nrd=0.031475 nrs=0.031475 sa=545.4200n sb=545.4200n sca=6.69814 \
        scb=0.00508037 scc=0.000303349 sa1=170.94300n sa2=442.04300n \
        sa3=735.1600n sa4=410.01400n sb1=170.94300n sb2=442.04300n \
        sb3=735.1600n spa=117.68700n spa1=117.6400n spa2=117.04600n \
        spa3=117.43400n sap=168.48100n sapb=194.36500n spba=163.57500n \
        spba1=170.96400n enx=1.68175u enx1=1.58702u eny=558.400n \
        eny1=390.97300n eny2=507.38900n rex=1.2283u rey=702.34300n \
        sa5=589.32800n sa6=710.87200n sodx=80n sodx1=339.84200n \
        sodx2=1.10182u sody=327.95200n dfm_flag=0 dw1=-1.33332e-20
.
. Many lines of netlist are truncated from here
.
. Just imagine what an extracted netlist might look like!
.
    M16 (start2 start1 vssa vssa) nch_18ud15_mac l=300n w=1u multi=1 nf=1 \
        sd=180.0n ad=7.5e-14 as=7.5e-14 pd=2.15u ps=2.15u nrd=0.09 \
        nrs=0.09 sa=75.0n sb=75.0n sca=9.21917 scb=0.00603396 \
        scc=0.000304546 sa1=75.0n sa2=75.0n sa3=75.0n sa4=75.0n sb1=75.0n \
        sb2=75.0n sb3=75.0n spa=100n spa1=100n spa2=100n spa3=100n \
        sap=91.97760n sapb=114.44400n spba=130.0n spba1=144.22200n \
        sa5=75.0n sa6=75.0n enx=800n enx1=800n eny=596.43500n \
        eny1=392.79900n eny2=507.38900n rex=938.73400n rey=754.77100n \
        sodx=80n sodx1=140.45700n sodx2=763.6600n sody=327.95200n
ends test_ckt
// End of subcircuit definition.

// Library name: test
// Cell name: tb_test_ckt
// View name: schematic
V0 (net2 0) vsource dc=supply_r type=dc
V1 (enable_bar 0) vsource dc=0 type=pulse val0=supply_r val1=0 period=1 \
        delay=enable_delay rise=100p fall=100p width=800.0m
V3 (start 0) vsource dc=start_vdc type=pwl wave=[ \
        (enable_delay+start_delay) 0 fin_time start_vdc ]
x0 (enable_bar start net2 out 0) test_ckt
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub

Now if the connectivity were just included since it already exists in the netlist file (yes, it's just named netlist, no extension)

------------------------- Second  Example - Desired input.scs---------------

 // Generated for: spectre
// Generated on: Aug 13 15:02:09 2010
// Design library name: test
// Design cell name: tb_test_ckt
// Design view name: schematic
simulator lang=spectre
global 0
parameters start_vdc=0.6 supply_r=1.2 start_delay=1n enable_delay=1n \
    fin_time=1.5u
include "/import/foundry/foundry_geom/pdk/datecode/../models/spectre/toplevel.scs" section=top_tt
//
//
// Just do an include of the netlist file to get all the connectivity
//
include "$HOME/path/blah/blah/simulation/tb_test_ckt/spectre/netlist"
//
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub

 That's less than 30 lines! Easy to read and understand without all the nitty gritty details of the devices.  

Now do you understand? Is this possible through any existing settings?

It's just a large duplication of information that already exists elsewhere.

For example, a simple testbench for a simple circuit produces an input.scs of over 400 lines (see truncated example below).  Just imagine if this were a larger circuit and I was using extracted views. Jeesh!

--------------------------- First  Example - Existing input.scs---------------

// Generated for: spectre
// Generated on: Aug 13 15:02:09 2010
// Design library name: test
// Design cell name: tb_test_ckt
// Design view name: schematic
simulator lang=spectre
global 0
parameters start_vdc=0.6 supply_r=1.2 start_delay=1n enable_delay=1n \
    fin_time=1.5u
include "/import/foundry/foundry_geom/pdk/datecode/../models/spectre/toplevel.scs" section=top_tt

// Library name: test
// Cell name: test_ckt
// View name: schematic
subckt test_ckt enable_bar ibandgap vddr vref vssa
    MN0 (start1 n1 vssa vssa) nch_mac l=1.5e-07 w=9u multi=1 nf=9 \
        sd=120.0n ad=4.75e-13 as=4.75e-13 pd=10.950u ps=10.950u \
        nrd=0.031475 nrs=0.031475 sa=545.4200n sb=545.4200n sca=6.69814 \
        scb=0.00508037 scc=0.000303349 sa1=170.94300n sa2=442.04300n \
        sa3=735.1600n sa4=410.01400n sb1=170.94300n sb2=442.04300n \
        sb3=735.1600n spa=117.68700n spa1=117.6400n spa2=117.04600n \
        spa3=117.43400n sap=168.48100n sapb=194.36500n spba=163.57500n \
        spba1=170.96400n enx=1.68175u enx1=1.58702u eny=558.400n \
        eny1=390.97300n eny2=507.38900n rex=1.2283u rey=702.34300n \
        sa5=589.32800n sa6=710.87200n sodx=80n sodx1=339.84200n \
        sodx2=1.10182u sody=327.95200n dfm_flag=0 dw1=-1.33332e-20
.
. Many lines of netlist are truncated from here
.
. Just imagine what an extracted netlist might look like!
.
    M16 (start2 start1 vssa vssa) nch_18ud15_mac l=300n w=1u multi=1 nf=1 \
        sd=180.0n ad=7.5e-14 as=7.5e-14 pd=2.15u ps=2.15u nrd=0.09 \
        nrs=0.09 sa=75.0n sb=75.0n sca=9.21917 scb=0.00603396 \
        scc=0.000304546 sa1=75.0n sa2=75.0n sa3=75.0n sa4=75.0n sb1=75.0n \
        sb2=75.0n sb3=75.0n spa=100n spa1=100n spa2=100n spa3=100n \
        sap=91.97760n sapb=114.44400n spba=130.0n spba1=144.22200n \
        sa5=75.0n sa6=75.0n enx=800n enx1=800n eny=596.43500n \
        eny1=392.79900n eny2=507.38900n rex=938.73400n rey=754.77100n \
        sodx=80n sodx1=140.45700n sodx2=763.6600n sody=327.95200n
ends test_ckt
// End of subcircuit definition.

// Library name: test
// Cell name: tb_test_ckt
// View name: schematic
V0 (net2 0) vsource dc=supply_r type=dc
V1 (enable_bar 0) vsource dc=0 type=pulse val0=supply_r val1=0 period=1 \
        delay=enable_delay rise=100p fall=100p width=800.0m
V3 (start 0) vsource dc=start_vdc type=pwl wave=[ \
        (enable_delay+start_delay) 0 fin_time start_vdc ]
x0 (enable_bar start net2 out 0) test_ckt
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub

Now if the connectivity were just included since it already exists in the netlist file (yes, it's just named netlist, no extension)

------------------------- Second  Example - Desired input.scs---------------

 // Generated for: spectre
// Generated on: Aug 13 15:02:09 2010
// Design library name: test
// Design cell name: tb_test_ckt
// Design view name: schematic
simulator lang=spectre
global 0
parameters start_vdc=0.6 supply_r=1.2 start_delay=1n enable_delay=1n \
    fin_time=1.5u
include "/import/foundry/foundry_geom/pdk/datecode/../models/spectre/toplevel.scs" section=top_tt
//
//
// Just do an include of the netlist file to get all the connectivity
//
include "$HOME/path/blah/blah/simulation/tb_test_ckt/spectre/netlist"
//
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub

 That's less than 30 lines! Easy to read and understand without all the nitty gritty details of the devices.  

Now do you understand? Is this possible through any existing settings?