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Import Digital design (std cells) into cadence ICFB and run simulations

ASICengg
Hi

I have a digital block with standard cells that I want to add to analog block and run simulations in the cadence ICFB “analog environment”.

I can successfully import the schematics in the cadence composer as the symbols of std cells are available from foundry. However, the symbols appear as black box.

The foundry also provided us with “.spi” “.cir” and “.gds” files for the standard cells which have device information.

I want to know how I should import the above files into cadence ICFB so that I can descend the heirarchy of schematics at the device level.

I also want to know how to run simulations on digital design in “analog environment” using the spectre models provided by the technology library.

Thanks

  • Hi ASICengg

    I am guessing that your "cir" file is a cdl netlist. You can import a cdl netlist as schematic using "File->Import->CDL" function in ciw. This will generate the schematics and symbols for each subckt in the netlist. Please refer to $CDSHOME/doc/transref/transref.pdf for more help on importing a cdl netlist. You will need a mapping file.

    If "digital design" means the a schematic created using the imported standard cells, then you simply need to start ADE using "Tools->Analog Design", add the spectre model files using "Setup->Model Libraries", set the analysis and start simulation. You can get more help at $CDSHOME/doc/anasimhelp/anasimhelp.pdf.

    If you meant simulating a real digital design (verilog/vhdl) using spectre models, then actually it cannot be done because spectre models are meant for transistor level designs and are not needed by verilog/vhdl codes. You will need to use our AMS Designer simulator for a mixed signal design.

    Best regards
    Quek

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