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Exporting Verilog netlist from Virtuoso Schematics

mingfatty
Hi Folks, I am using Virtuoso 5.1.41 to perform my simulation (delay, power and etc) and hoping to export the end design in Verilog form so that i ca use encounter to do the place and route for me. I could not find the option in the virtuoso and please kindly help on this issue. Many thanks in advance. Best regards, Ming Fatt
  • Andrew Beckett

    Tools->Verilog Integration->NC Verilog (in the CIW).

    There's a similar menu under Tools from the schematic. 

    Regards,

    Andrew.

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