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How to speed up verilog ams?

I am using Cadence Verilog-AMS simulator on a design (digital portion is about 230K gates, analog portion is 100 transistors.).

It seems that the following steps are taking exceedingly long (much longer than the actual transient simulation itself):

1) ### Generating design information at:/storage/wtam/TestBench/ams/config/netlist ###
2) Elaborating analog portion of the design hierarchy

Can I know what is going on during these steps? And how can I speed it up?

Thanks a lot!!

Quek over 14 years ago

Hi Wing2

It would be better if you can upload your log files so that everyone can have more clues to your problems. : ) Please upload as file attachments, not cut and paste.

Best regards
Quek
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