Stats

Locked Locked
Replies 1
Subscribers 125
Views 13555
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Parasitic EXtraction of an interconnect capacitance

Ueue over 14 years ago

Hi all,

I am trying to create an interconnect capacitance in my circuit.

So I created a schematic view with only the PINs (PLUS and MINUS) and I created the layout of the cell.

My aim is to extract the parasitics for having a schematic to use in simulations.

The problem is that, when I try to run the Calibre PEX (as for the LVS), I get:

"ERROR: Nothing in source.

ERROR: Nothing in layout. "

How can I solve the problem of extracting the parasitics from my cell?

Thanks,

Stefano

Andrew Beckett over 14 years ago

Hi Stefano,
Since Calibre PEX and Calibre LVS are tools from Mentor Graphics, not Cadence, you might be better off asking this on a Mentor forum?
Regards,
Andrew.
Cancel
Vote Up 0 Vote Down

Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.