Stats

  • Locked Locked
  • Replies 12
  • Subscribers 128
  • Views 18291
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Porting Layout is Virtuoso Layout to Encounter

nick83

Hi all,

I am new to this forum. I have recently started integrating my first test chip.

I have following problem:

My analog block is laid out in Virtuoso Layout editor and by digital block in Encounter.

How can I port my layout from Virtuoso Layout editor to Encounter. I am very new to Encounter. Can any one tell me some method by which I can port my design from layout editor to encounter where I can combine the two blocks?

Please provide me your suggestions and inputs.

Regards

Nick

Parents

  • Hi Quek,

    I am confusing with generating LEF in IC614 for my cell layouts for the P&R purpose. I notice that File->Export->LEF can simply generate LEF for cells without complicated steps as Abstract Generator. But by reading the LEF file it seems that the tech process infomation is not included, but only some layout geometry information like "width" and "spacing". I guess this file is not readable in SoC encounter (now called EDI?). So is AG the only way to generate necessary file for P&R tool? Actually I am having trouble on starting AG. Some errors in the log said like:

     ERROR     (ABS-216): There are insufficient metal layers defined in the current design. You must define at least two metal layers in the validLayers subsection of LEFDefaultRouteSpec  constraint group of the technology file. These layers must have the layer function "metal" in the functions section. Update the technology file and attach it again.

    ERROR     (ABS-218): There are no vias specified in the technology file. Ensure that the selected constraint group has a ValidVias section or at least one via is specified in the standardViaDefs subsection of the viaDefs section in the technology file. In addition, ensure that the function argument is set to 'cut' for the via in the functions subsection of the layerRules section and then try again.
     
    INFO      (ABS-232): Layer summary: 0 metal layer(s), 0 via layer(s), 1 poly layer(s), and 1 diff layer(s) found
    INFO      (ABS-234): Via summary: 0 valid via(s) found
     
    Is there anything I am missing for the tech defination?
    Thanks in advance.
    bjbit 
Reply

  • Hi Quek,

    I am confusing with generating LEF in IC614 for my cell layouts for the P&R purpose. I notice that File->Export->LEF can simply generate LEF for cells without complicated steps as Abstract Generator. But by reading the LEF file it seems that the tech process infomation is not included, but only some layout geometry information like "width" and "spacing". I guess this file is not readable in SoC encounter (now called EDI?). So is AG the only way to generate necessary file for P&R tool? Actually I am having trouble on starting AG. Some errors in the log said like:

     ERROR     (ABS-216): There are insufficient metal layers defined in the current design. You must define at least two metal layers in the validLayers subsection of LEFDefaultRouteSpec  constraint group of the technology file. These layers must have the layer function "metal" in the functions section. Update the technology file and attach it again.

    ERROR     (ABS-218): There are no vias specified in the technology file. Ensure that the selected constraint group has a ValidVias section or at least one via is specified in the standardViaDefs subsection of the viaDefs section in the technology file. In addition, ensure that the function argument is set to 'cut' for the via in the functions subsection of the layerRules section and then try again.
     
    INFO      (ABS-232): Layer summary: 0 metal layer(s), 0 via layer(s), 1 poly layer(s), and 1 diff layer(s) found
    INFO      (ABS-234): Via summary: 0 valid via(s) found
     
    Is there anything I am missing for the tech defination?
    Thanks in advance.
    bjbit 
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.