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Hierarchical Parasitic Extraction & Cadence Tools

jimito13

Hello Everyone,

I have come up with a question and i would really want to hear the opinion of more expert people in here about my issue concerning parasitic extraction in an hierarchical design.So,let me pose my question more clearly :

I have an hierarcical design.Let's say that the top level schematic's name is A.

A consists of two sub-cells that i will give them the name B1,B2.

B1 has 6 more sub-cells (C1,C2,C3,C4,C5,C6).

I know hot to perform hierarchical RCX with the Hierarchy Editor tool of Cadence but...if i want to take into account the parasitics of the interconnections of some specific sub-cells what is the way to implement the extraction procedure and take correct results?Can Hierarchy Editor do this or i need another tool of cadence and subsequently an extra license for this?

A testbench for me in the hierarchy editor would be :

A -->Schematic

B1 -->Schematic

C1,C2,C3,C4 -->Schematic

C5,C6 --> av_extracted

B2 -->av_extracted

and i want to extract as well the interconnections between C5-C6 cells and between B1-B2 cells.I should note that all sub-cells have their own physical implementation (layout view in other words).

Thanks in advance for any helpful answer.

My Best Regards,

Jimito13

 

Parents

  • Hello Quek,

    Thanks a lot for your helpful feedback :-) You are absolutely right with your first paragraph,QRC performs the extraction procedure and not HE,i formulated it wrong in my first message.I have a couple of additional questions before closing this topic.

    1. ?preserveCells gives a drop-down menu with File & Cells choises.What should i select?Sould i syntax a file and input it into Assura via the menu below or i can insert the names of the cells manually?I would appreciate if you could send me a screenshot as an example or an example syntax of a file.

    2.The Vss rail of my circuit is one and common to all cells from the lowest level to the top level via various interconnections from level to level.Is it possible to exclude it from extraction of some specific cells and not from others?I suppose that it is not feasible since in reality Vss i one entity (irrelevantly if it is created from Vss cables of individual low level cells and the interconnections among them) but i am wondering if there is a technique to cheat Assura QRC and make the selective extraction i desire...

    Thanks in advance.

    Best Regards,

    Jimito13

Reply

  • Hello Quek,

    Thanks a lot for your helpful feedback :-) You are absolutely right with your first paragraph,QRC performs the extraction procedure and not HE,i formulated it wrong in my first message.I have a couple of additional questions before closing this topic.

    1. ?preserveCells gives a drop-down menu with File & Cells choises.What should i select?Sould i syntax a file and input it into Assura via the menu below or i can insert the names of the cells manually?I would appreciate if you could send me a screenshot as an example or an example syntax of a file.

    2.The Vss rail of my circuit is one and common to all cells from the lowest level to the top level via various interconnections from level to level.Is it possible to exclude it from extraction of some specific cells and not from others?I suppose that it is not feasible since in reality Vss i one entity (irrelevantly if it is created from Vss cables of individual low level cells and the interconnections among them) but i am wondering if there is a technique to cheat Assura QRC and make the selective extraction i desire...

    Thanks in advance.

    Best Regards,

    Jimito13

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