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Hierarchical Parasitic Extraction & Cadence Tools

jimito13

Hello Everyone,

I have come up with a question and i would really want to hear the opinion of more expert people in here about my issue concerning parasitic extraction in an hierarchical design.So,let me pose my question more clearly :

I have an hierarcical design.Let's say that the top level schematic's name is A.

A consists of two sub-cells that i will give them the name B1,B2.

B1 has 6 more sub-cells (C1,C2,C3,C4,C5,C6).

I know hot to perform hierarchical RCX with the Hierarchy Editor tool of Cadence but...if i want to take into account the parasitics of the interconnections of some specific sub-cells what is the way to implement the extraction procedure and take correct results?Can Hierarchy Editor do this or i need another tool of cadence and subsequently an extra license for this?

A testbench for me in the hierarchy editor would be :

A -->Schematic

B1 -->Schematic

C1,C2,C3,C4 -->Schematic

C5,C6 --> av_extracted

B2 -->av_extracted

and i want to extract as well the interconnections between C5-C6 cells and between B1-B2 cells.I should note that all sub-cells have their own physical implementation (layout view in other words).

Thanks in advance for any helpful answer.

My Best Regards,

Jimito13

 

  •  Hi Jimito13,

    Each cellView that you're picking in the hierarchy editor will have nets and components as contained in that cellView. So for example, if your av_extracted view has parasitic R and C on some nets, those will be included in the design being netlisted.

    Nothing additional will get invented, if you like. You simply are netlisting the components and connectivity in the cellViews you've picked. 

    So, any ideal blocks you have will be ideal. Any parasitic extracted blocks you have will have parasitics. This strikes me as being rather obvious, so I'm not quite sure why you're asking this? All the hierarchy editor does is allow you to choose which representations will be used for each cell, or instance (or occurrence) in the hierarchy, and is used by the netlisters so they know which blocks to netlist as the hierarchy is traversed.

    Regards,

    Andrew.

  • Hello Andrew,

    Thanks for your reply at first.Maybe i didn't pose my question clear enough at first.What you say is absolutely obvious so it would never be the subject of a question.Suppose that i have a cell A with schematic representation and cell B with av_extracted representation during simulation with HE of the top level cell C (A,B and their interconnection are the cells that create the top level circuit C).How the simulator is going to consider the connection between A and B if the configuration is as mentioned above (A-->Schematic , B-->av_extracted)?

    Thanks in advance.

    My Best Regards,

    Jimito13

  • Presumably for a particular net which exists in cell A, cell B and also in the top level C (i.e. the connection between the instances), you'll have the parasitics on that net which exist in cell B, the ideal connections that  you have in cell A, and whatever components on that net which come from cell C.

    This still seems fairly obvious, so I must be missing something still...

    Perhaps you should try it and take a look at the resulting netlist? That may clarify any confusion or concerns you may have?

    Regards,

    Andrew.

  • Hi Jimito13

    I think Andrew has already explained the key point. You will get whatever that is in the view which you have set in HE. We have the following situation:

    Top cell C contains 2 cells A and B. In HE, cell A uses schematic view and B uses av_extracted view. C is a schematic.

    Since C is a schematic, there are no parasitics in the line connecting cells A and B. Simulator does not need to be concerned about this situation because this is the job of the netlister. Here is what you will get:

    a. Netlister writes connection between A and B as ideal connection
    b. It descends into schematic view of cell A and netlist the devices
    c. It descends into av_extracted view of cell B and netlist the devices and parasitic RCs

    Hope that this clears up your confusion. : )

    Best regards
    Quek

  • Ok guys i got it now.Maybe my confusion was indeed obvious but i just wanted some confirmation.Thanks a lot for your time and your precious answers.

    My Best Regards,

    Jimito13

  • Don't worry - there are many things that only appear obvious once you've fully understood them!

    Regards,

    Andrew.

  •  Hi, Quek,

     I come cross this topic, and this is assura QRC flow, but now I am running PVS QRC flow, what is the same function to preserve cells in PVS LVS?

     Best regards

    Jingnan

     

  • Hi Jingnan

    You can use "hcell" file during pvs lvs. E.g.

    layoutCellA schCellB
    ...

    layoutCellA will be matched to schCellB.


    Best regards
    Quek

  •  Hi, Quek,

    Thanks! One error appeared when I run hierarchical QRC is below,

     Error: Failed to create terminal cpump_nonoverlaping_clocks_0/I150/net38
    *WARNING* (DB-270000): dbCreateTerm: Invalid character '/' in input name: cpump_nonoverlaping_clocks_0/I150/net38
    INFO (LBRCXU-111): Warning /home/id_pn548/cadenv/cadenv_frontend_oa/.caddata/cadence_ic/bin/qrcToDfII exit with bad status

    INFO (LBRCXU-112): Warning Status 256

    INFO (LBRCXU-113): Warning QRC execution terminated


    *****  aveng fork terminated abnormally  *****

    Do you have any clue why?

    Best regards

     Jingnan

     

     

     

  • Hi Jingnan

    As suggested by the error message, there should not be "/" in the net name. I think the error should go away if you avoid using "/" in the net names.


    Best regards
    Quek

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