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  3. Hierarchical Parasitic Extraction & Cadence Tools

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Hierarchical Parasitic Extraction & Cadence Tools

jimito13
jimito13 over 14 years ago

Hello Everyone,

I have come up with a question and i would really want to hear the opinion of more expert people in here about my issue concerning parasitic extraction in an hierarchical design.So,let me pose my question more clearly :

I have an hierarcical design.Let's say that the top level schematic's name is A.

A consists of two sub-cells that i will give them the name B1,B2.

B1 has 6 more sub-cells (C1,C2,C3,C4,C5,C6).

I know hot to perform hierarchical RCX with the Hierarchy Editor tool of Cadence but...if i want to take into account the parasitics of the interconnections of some specific sub-cells what is the way to implement the extraction procedure and take correct results?Can Hierarchy Editor do this or i need another tool of cadence and subsequently an extra license for this?

A testbench for me in the hierarchy editor would be :

A -->Schematic

B1 -->Schematic

C1,C2,C3,C4 -->Schematic

C5,C6 --> av_extracted

B2 -->av_extracted

and i want to extract as well the interconnections between C5-C6 cells and between B1-B2 cells.I should note that all sub-cells have their own physical implementation (layout view in other words).

Thanks in advance for any helpful answer.

My Best Regards,

Jimito13

 

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  • Jingnan
    Jingnan over 12 years ago

     Hi, Quek,

    This is a net from lower level instance, it has to be with "/", how can I remove it?

    Best regards

    Jingnan

     

     

     

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  • Quek
    Quek over 12 years ago

    Hi Jingnan

    Did you specify "/" as the hierarchy delimiter in the qrc cmd file? E.g.

    output_db \
    -type spice \
    -hierarchy_delimiter "/"

    Actually your question is not really related to this thread so it would be great if you can start a new thread whenever you have a new issue. This would help all forum readers in following the issues. : )


    Best regards
    Quek

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  • GabrielB
    GabrielB over 11 years ago

    Hallo everyone,

    I'm sorry to start with this topic again, but it seems you are the only ones in the web who have faced the same problem as me.

    I'm trying also to make a hierarchical extraction with QRC since I'm interested in the parasitic of the connection lines between pads and core: I'd like then to simulate all the subcells, and maybe the pads too, at schematic or functional level.

    So let's say my top cell A is made of subcells B1 (multiplexer with shor-circuited inputs) , B2 (level shifter) and B3 (digital pad), which form a chain, I use Assura LVS with the ?preserveCell option and the list of the cells. Then with the same list I use H-QRC.

    My problem is: for every (preserved) cell a new cell and in case a new library (with "library prefix") are created. So that in the HE I cannot change the cell view back to schematic, as I would like too. 

    So I tryed the option "+ netlist=none" for QRC hierarchical extraction and so I can set a schematic view in the HE. 

    However this result has some troubles - there is no way to netlist it (e.g. neither with ADE nor with CDL export), I guess since the terminals of B1, B2 and B3 don't match with the description.

    Am I missing some steps? Maybe some easy options in the LVS schematic netlisting? Actually if I have a look at the internal Assura LVS database with VdbToCdl i can see that cells B1, B2 and B3 were preserved, but the terminal definitions are different from the original ones...

    I really hope you'll be able to help me, in each case, thanks in advance for reading!

    Gabriel

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  • GabrielB
    GabrielB over 11 years ago

    Here are some errore messages to make it more clear.

    Trying to netlist a testbench with ADE spectre and config view:

    Netlist Error: Conflict between symbol view and schematic view of instance "I2" in cell-view "ext_WORKBENCHES_NCG" "INV_ROUTING_and_PAD_rcx" "ae_RC"

    Trying to export a CDL netlist of previous config view:

    WARNING (AUCDL-43): Terminal IN0 appearing in CDF termOrder for component : MU4LJI3VX1

    in cellview : layout

    of library : D_CELLSL_JI3V

    is invalid.

    Ensure that this CDF has same terminal names as specified in this cell view.

    Nets will be printed in default terminal order for this component.

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