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Verilog Import

Dear ALL,

The digital part of the chip has a verilog netlist. The power and ground ports are not global but the standard cells have global power and ground ports (VDD! and VSS!). What should I do to make the output schematic connect the internal VDD! and VSS! to the output vdd and gnd ports (let their names be clkgen_vdd clkgen_gnd)?

Also the verilog netlist has input busses defined as: "\in<1>", but when it is imported it define the port as "in#3c1#3e". Is there an option to overcome this worng translation?

Thanks and Best Regards,

Mohamed Samir

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