Automatic Place and Route for a standard cell design using a single metal layer only

 Hallo all,

           I have designed the schematic of a relatively small circuit using sinmple digital blocks like MUX, DFF, INV etc (220 transistors) and simulated it. But we have now been provided with standard cells for all of these digital blocks. These standard cells have inputs and outputs at the top and bottom of the cells . Now I need to make the layout of this, but using just a single metal layer (not even polysilicon layer) which should be 20um wide and 20um spacing. Is it possible for me to do the layout automatically in cadence? It would be helpful if somebody can help me in creating the required files for DRC, LVS etc.