errors during LVS with RF Transistors @ IBM cms9flp pdk

Hello all,

I perform LVS with assura tool (IC6131-Assura 3.2) on my design that consists of nfet_rf & pfet_rf transistors (only this type and nothing else like capacitors,regular fets etc...) from IBM rf9flp library (part of cms9flp design kit) and i have a lot of errors concerning the sub! and VSS (ground) terminals.

I must note that i have removed the substrate and nwell contact rings around the transistors (nmos and pmos respectively) and i have created my own rings for the whole design.

It is very important to me for a fast solution and IBM's technical support team doesn't seem to cooperate for a solution...Let me be more specific with my problem.

I had created a simple test case with nfet_rf from rf9flp library that consists of a single nfet_rf and no subc in the schematic.In addition i removed the default guard ring of the nfet_rf.At the layout side i have the transistor and a subc component.This case passes VLDB LVS and according to IBM's team it is ok and they are working on a solution after my report to them.

Now,let's see the design.It consists of various nfet_rf (only this type of transistor and nothing else like capacitors,regular fets etc...).At the schematic side i use subc (same results if i don't use it since IBM admitted that it causes problem if it exists) and i have removed the default guard ring with substrate contacts of all fets because i create a custom one for all the nmos area in the layout.
Then i run VLDB LVS and i will show you the errors (rewires,nets) via the LVS.cls file below.If anymore info are needed for a conclusion i will provide them.

Thanks a lot in advance.I will appreciate any helpful feedback since it is very critical issue for me.

Best Regards,

Jimito13

*******************************************************************************
****** ota_main_rf_2 schematic Dimitris_initial  <vs>  ota_main_rf_2 layout Dimitris_initial
*******************************************************************************
                                                                                                                                                                                                                           
Pre-expand Statistics                     
======================                          Original      
Cell/Device                               schematic  layout
(lvtpfet_rf) Generic                              2       2
(pfet_rf) Generic                                13      13
(nfet_rf) Generic                                 9       9
(subc) Generic                                    1    1980*
                                             ------  ------
Total                                            25    2004

Filter Statistics
=================                               Original            Filtered
Cell/Device                               schematic  layout   schematic  layout
(lvtpfet_rf) Generic                              2       2           2       2
(nfet_rf) Generic                                 9       9           9       9
(pfet_rf) Generic                                13      13          13      13
(subc) Generic                                    1    1980*          1    1980*

Reduce Statistics
=================                               Filtered             Reduced
Cell/Device                               schematic  layout   schematic  layout
(lvtpfet_rf) Generic                              2       2           2       2
(nfet_rf) Generic                                 9       9           9       9
(pfet_rf) Generic                                13      13           9       9
(subc) Generic                                    1    1980*          1       1

Match Statistics
================                                  Total             Unmatched
Cell/Device                               schematic  layout   schematic  layout
(lvtpfet_rf) Generic                              2       2           0       0
(nfet_rf) Generic                                 9       9           0       0
(pfet_rf) Generic                                 9       9           0       0
(subc) Generic                                    1       1           0       0
                                             ------  ------      ------  ------
Total                                            21      21           0       0

Match Statistics for Nets                        22      30           1       9

================================================================[ota_main_rf_2]
====== Bad Initial Net Bindings (nets don't match) ============================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 1)
Schematic Net:  GND
S       1   of subc SUBCON
S       7   of nfet_rf S

Layout Net:  GND
L       1   of subc SUBCON
L      *1   of subc sub
L       7   of nfet_rf S

================================================================[ota_main_rf_2]
====== Unmatched Internal Nets ================================================
===============================================================================

L ?avS8513
L ?avS8512
L ?avS8510
L ?avS8516
L ?avS8517
L ?avS8514
L ?avS8515
L ?avS8509
L ?avS8511

================================================================[ota_main_rf_2]
====== Suggested Terminal Rewire ==============================================
===============================================================================

In the layout, terminal 'B' of instance avD20_7 probably should connect to net
avS8512 instead of net avS8515.
This makes a better match between layout net avS8512 and schematic net sub!.

In the layout, terminal 'B' of instance avD20_3 probably should connect to net
avS8512 instead of net avS8510.
This makes a better match between layout net avS8512 and schematic net sub!.

In the layout, terminal 'B' of instance avD20_4 probably should connect to net
avS8512 instead of net avS8516.
This makes a better match between layout net avS8512 and schematic net sub!.

In the layout, terminal 'B' of instance avD20_9 probably should connect to net
avS8512 instead of net avS8511.
This makes a better match between layout net avS8512 and schematic net sub!.

In the layout, terminal 'B' of instance avD20_1 probably should connect to net
avS8512 instead of net avS8513.
This makes a better match between layout net avS8512 and schematic net sub!.

In the layout, terminal 'B' of instance avD20_5 probably should connect to net
avS8512 instead of net avS8517.
This makes a better match between layout net avS8512 and schematic net sub!.

In the layout, terminal 'B' of instance avD20_8 probably should connect to net
avS8512 instead of net avS8509.
This makes a better match between layout net avS8512 and schematic net sub!.

In the layout, terminal 'B' of instance avD20_6 probably should connect to net
avS8512 instead of net avS8514.
This makes a better match between layout net avS8512 and schematic net sub!.

In the layout, terminal 'sub' of instance avD226_1 probably should connect to
net avS8512 instead of net GND.
This makes a better match between layout net avS8512 and schematic net sub!.

================================================================[ota_main_rf_2]
====== Problem Schematic Nets (no exact match in layout) ======================
===============================================================================
S
S ?GND
S       1   of subc SUBCON
S       7   of nfet_rf S
S
S ?sub!
S       1   of subc sub
S       9   of nfet_rf B

================================================================[ota_main_rf_2]
====== Problem Layout Nets (no exact match in schematic) ======================
===============================================================================
L
L ?avS8513 ?avS8512 ?avS8510 ?avS8516 ?avS8517 ?avS8514 ?avS8515 ?avS8509
L ?avS8511
L (total 9) with:
L       1   of nfet_rf B
L
L ?GND
L       1   of subc SUBCON
L       1   of subc sub
L       7   of nfet_rf S

================================================================[ota_main_rf_2]
====== Summary of Errors ======================================================
===============================================================================

Schematic  Layout     Error Type
---------  ------     ----------
 1          1         Bad Initial Net Bindings
 -          9         Suggested Terminal Rewire
 -          9         Unmatched Internal Nets