Stats

  • Locked Locked
  • Replies 0
  • Subscribers 125
  • Views 12776
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

modifying the connectivity in Technology file without effecting the existing VIA layers

sandroji

Dear Andrew,

I have a tech file with the following layer stack,

MET6,VIA5,MIM,MET5,VIA4,MET4,VIA3,MET3.

std vias are defined as :

MET6/VIA5/MET5

MET5/VIA4/MET4

MET4/VIA3/MET3

 

When placing a MIM capacitor in the layout and applying marknet to a net which contains one of the MIM cap terminals , i get a short thought the MIM Capacitor.

Is there a way to redefine the connectivity without using STOP layers (on the input layers i mean)? , in order to prevent this false short from effecting the markNet result.

 I dont want to replace any layers in the tech file or do any change which might effect existing designs.

 Thank you for your support and great source of information

Alex

 

 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.