Simulation settings

Hi, I am designing an all digital pll using cadence 6.1.4. It is taking about 10 us to lock the output. When I am trying to run my simulation that long it is taking 3-4 days. I tried using aps simulation (errpreset = liberal) instead of spectre and could decrease the simulation time to 1 day. I am also saving only the outputs that are required not all. Are there any more options I can change to further decrease my simulation time. I also need to give the output of the above pll as an input to another circuit. Can someone help me out if there is a way to save the outputs of pll and give it as an input stimuli to the other circuit so that i can simulate those circuits individually. Thanks, Muppala.