QRC Parasitic Extraction Issue (netlist has source/drain flipped on many instances)

Hi,

   I am working on a analog design in Cadence IC6.1.4.500.5, and I have completed the layout of the chip with DRC, LVS, floating gate check that is clean (I amworking with IBM's CMRF7SF process).After I ran Assura QRC to generate av_extracted, and av_analog_extracted views I go back into my testbenches to run toplevel sims with these new views, and I am running into problems.

   I am comparing the netlist with extracted views, and I noticed that on many of the NMOS and PMOS devices, the source and drain is flipped from what I intended them to be in my design. For example, I expect N1 to have a netlist of N1(D G S B) according to my schematics, and instead of that, the parasitic netlist of the instance N1 has a netlist of N1(S G D B). Wondering why that's the case. I passed LVS, and this only shows up in av_extracted and analog_av_extracted views... Thanks for any tip/advice from you!